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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id 10-20020ac2484a000000b004a2c447598fsm147065lfy.159.2023.03.30.17.39.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 Mar 2023 17:39:09 -0700 (PDT) Message-ID: <48ac39ed-cb14-a07a-447f-b1022c44737e@linaro.org> Date: Fri, 31 Mar 2023 03:39:08 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH v2 2/5] drm/msm/a6xx: Add support for A650 speed binning Content-Language: en-GB To: Konrad Dybcio , linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Rob Clark , Abhinav Kumar , Sean Paul , David Airlie , Daniel Vetter , Akhil P Oommen , Chia-I Wu , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20230120172233.1905761-1-konrad.dybcio@linaro.org> <20230120172233.1905761-3-konrad.dybcio@linaro.org> From: Dmitry Baryshkov In-Reply-To: <20230120172233.1905761-3-konrad.dybcio@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 20/01/2023 19:22, Konrad Dybcio wrote: > Add support for matching QFPROM fuse values to get the correct speed bin > on A650 (SM8250) GPUs. > > Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Thank you for the patch. It took me a while to dive into various ways vendor kernels handle GPU speed bins. > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 0ee8cb3e490c..c5f5d0bb3fdc 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -1894,6 +1894,20 @@ static u32 a640_get_speed_bin(u32 fuse) > return UINT_MAX; > } > > +static u32 a650_get_speed_bin(u32 fuse) > +{ > + if (fuse == 0) > + return 0; > + else if (fuse == 1) > + return 1; > + else if (fuse == 2) > + return 2; > + else if (fuse == 3) > + return 3; > + > + return UINT_MAX; > +} > + > static u32 adreno_7c3_get_speed_bin(u32 fuse) > { > if (fuse == 0) > @@ -1922,6 +1936,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) > if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) > val = a640_get_speed_bin(fuse); > > + if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) > + val = a650_get_speed_bin(fuse); > + > if (val == UINT_MAX) { > DRM_DEV_ERROR(dev, > "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", -- With best wishes Dmitry