From: <Conor.Dooley@microchip.com>
To: <zong.li@sifive.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <palmer@dabbelt.com>,
<paul.walmsley@sifive.com>, <aou@eecs.berkeley.edu>,
<greentime.hu@sifive.com>, <ben.dooks@sifive.com>, <bp@alien8.de>,
<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 4/6] soc: sifive: ccache: reduce printing on init
Date: Mon, 5 Sep 2022 18:36:15 +0000 [thread overview]
Message-ID: <490336f2-5028-499f-d78f-620e083b3c61@microchip.com> (raw)
In-Reply-To: <20220905083125.29426-5-zong.li@sifive.com>
On 05/09/2022 09:31, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> From: Ben Dooks <ben.dooks@sifive.com>
>
> The driver prints out 6 lines on startup, which can easily be redcued
> to two lines without losing any information.
>
> Note, to make the types work better, uint64_t has been replaced with
> ULL to make the unsigned long long match the format in the print
> statement.
>
> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
Hey Zong,
Missing your SoB after Ben's here btw.
> ---
> drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++--------------
> 1 file changed, 11 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> index 0e0eb85c94d8..401c67a485e2 100644
> --- a/drivers/soc/sifive/sifive_ccache.c
> +++ b/drivers/soc/sifive/sifive_ccache.c
> @@ -81,20 +81,17 @@ static void setup_sifive_debug(void)
>
> static void ccache_config_read(void)
> {
> - u32 regval, val;
> -
> - regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> - val = regval & 0xFF;
> - pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
> - val = (regval & 0xFF00) >> 8;
> - pr_info("CCACHE: No. of ways per bank: %d\n", val);
> - val = (regval & 0xFF0000) >> 16;
> - pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
> - val = (regval & 0xFF000000) >> 24;
> - pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
> -
> - regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> - pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
> + u32 cfg;
> +
> + cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> +
> + pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
> + (cfg & 0xff), (cfg >> 8) & 0xff,
> + BIT_ULL((cfg >> 16) & 0xff),
> + BIT_ULL((cfg >> 24) & 0xff));
Could we use defines please for the register shifts please?
> +
> + cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> + pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);
%u here no?
Thanks,
Conor.
> }
>
> static const struct of_device_id sifive_ccache_ids[] = {
> --
> 2.17.1
>
next prev parent reply other threads:[~2022-09-05 18:36 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-05 8:31 [PATCH v2 0/6] Use composable cache instead of L2 cache Zong Li
2022-09-05 8:31 ` [PATCH v2 1/6] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Zong Li
2022-09-05 18:02 ` Conor.Dooley
2022-09-08 21:21 ` Rob Herring
2022-09-08 21:32 ` Conor.Dooley
2022-09-05 8:31 ` [PATCH v2 2/6] soc: sifive: ccache: Rename SiFive " Zong Li
2022-09-05 18:10 ` Conor.Dooley
2022-09-06 1:52 ` Zong Li
2022-09-05 18:46 ` Conor.Dooley
2022-09-06 1:44 ` Zong Li
2022-09-06 6:23 ` Conor.Dooley
2022-09-06 6:51 ` Zong Li
2022-09-05 8:31 ` [PATCH v2 3/6] soc: sifive: ccache: determine the cache level from dts Zong Li
2022-09-05 18:14 ` Conor.Dooley
2022-09-06 1:57 ` Zong Li
2022-09-05 8:31 ` [PATCH v2 4/6] soc: sifive: ccache: reduce printing on init Zong Li
2022-09-05 18:36 ` Conor.Dooley [this message]
2022-09-06 1:40 ` Zong Li
2022-09-05 8:31 ` [PATCH v2 5/6] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Zong Li
2022-09-05 18:44 ` Conor.Dooley
2022-09-06 1:38 ` Zong Li
2022-09-05 8:31 ` [PATCH v2 6/6] EDAC/sifive: use sifive_ccache instead of sifive_l2 Zong Li
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=490336f2-5028-499f-d78f-620e083b3c61@microchip.com \
--to=conor.dooley@microchip.com \
--cc=aou@eecs.berkeley.edu \
--cc=ben.dooks@sifive.com \
--cc=bp@alien8.de \
--cc=devicetree@vger.kernel.org \
--cc=greentime.hu@sifive.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-edac@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=zong.li@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).