From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753347AbdHJVRP (ORCPT ); Thu, 10 Aug 2017 17:17:15 -0400 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:56981 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752894AbdHJVRN (ORCPT ); Thu, 10 Aug 2017 17:17:13 -0400 From: Chris Packham To: Rob Herring CC: "gregory.clement@free-electrons.com" , "bp@alien8.de" , "jlu@pengutronix.de" , "linux-arm-kernel@lists.infradead.org" , "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Mark Rutland , "devicetree@vger.kernel.org" Subject: Re: [RESEND PATCH 2/4] dt-bindings: add "reduced-width" property for Armada XP SDRAM controller Thread-Topic: [RESEND PATCH 2/4] dt-bindings: add "reduced-width" property for Armada XP SDRAM controller Thread-Index: AQHTDx8J+wRJYRRytUetvg7ztLN6BQ== Date: Thu, 10 Aug 2017 21:17:10 +0000 Message-ID: <4935472b6a44447fa764fa811a645b9f@svr-chch-ex1.atlnz.lc> References: <20170807014641.4003-1-chris.packham@alliedtelesis.co.nz> <20170807014641.4003-3-chris.packham@alliedtelesis.co.nz> <20170810203801.jz5hl5onqci275ef@rob-hp-laptop> Accept-Language: en-NZ, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [2001:df5:b000:22:3a2c:4aff:fe70:2b02] Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by nfs id v7ALHLFa014588 On 11/08/17 08:38, Rob Herring wrote: > On Mon, Aug 07, 2017 at 01:46:39PM +1200, Chris Packham wrote: >> Some SoC implementations that use this controller have a reduced pin >> count so the meaning of "full" and "half" with change. > > s/with/width/ ? > Yes will include in v2. >> >> Signed-off-by: Chris Packham >> --- >> .../bindings/memory-controllers/mvebu-sdram-controller.txt | 6 ++++++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt b/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt >> index 89657d1d4cd4..3041868321c8 100644 >> --- a/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt >> +++ b/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt >> @@ -13,6 +13,12 @@ Required properties: >> - reg: a resource specifier for the register space, which should >> include all SDRAM controller registers as per the datasheet. >> >> +Optional properties: >> + - marvell,reduced-width: some SoCs that use this SDRAM controller have >> + a reduced pin count. On such systems "full" width is 32-bits and >> + "half" width is 16-bits. Set this property to indicate that the SoC >> + used is such a system. > > Maybe you should just state what the width is. Specifying a number like 64/32/16 is done in for some other properties I dismissed that because what this is about how we interpret a pin-strapping option. I guess "max-width = <64>;" and "max-width = <32>"; would achieve the same. > Or your compatible string should just be specific enough to know the > width. I decided against a new compatible sting that because the IP block really is the Armada-XP one and the existing compatible string is used in other places (using multiple compatible strings would solve that). I'm not too fussed which of the 3 options are used. Is there any particular preference?