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([2600:1010:b062:827f:f4a7:a1e:b790:5671]) by smtp.gmail.com with ESMTPSA id 1sm3927505pgp.88.2019.11.21.11.01.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Nov 2019 11:01:41 -0800 (PST) Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable From: Andy Lutomirski Mime-Version: 1.0 (1.0) Subject: Re: [PATCH v10 6/6] x86/split_lock: Enable split lock detection by kernel parameter Date: Thu, 21 Nov 2019 11:01:39 -0800 Message-Id: <4BB1CB74-887B-4F40-B3B2-F0147B264C34@amacapital.net> References: <20191121185303.GB199273@romley-ivt3.sc.intel.com> Cc: Andy Lutomirski , David Laight , Ingo Molnar , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , Borislav Petkov , H Peter Anvin , Tony Luck , Ashok Raj , Ravi V Shankar , linux-kernel , x86 In-Reply-To: <20191121185303.GB199273@romley-ivt3.sc.intel.com> To: Fenghua Yu X-Mailer: iPhone Mail (17A878) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Nov 21, 2019, at 10:40 AM, Fenghua Yu wrote: >=20 > =EF=BB=BFOn Thu, Nov 21, 2019 at 09:51:03AM -0800, Andy Lutomirski wrote: >>> On Thu, Nov 21, 2019 at 9:43 AM David Laight w= rote: >>>=20 >>> From: Ingo Molnar >>>> Sent: 21 November 2019 17:12 >>>> * Peter Zijlstra wrote: >>> ... >>>>> This feature MUST be default enabled, otherwise everything will >>>>> be/remain broken and we'll end up in the situation where you can't use= >>>>> it even if you wanted to. >>>>=20 >>>> Agreed. >>>=20 >>> Before it can be enabled by default someone needs to go through the >>> kernel and fix all the code that abuses the 'bit' functions by using the= m >>> on int[] instead of long[]. >>>=20 >>> I've only seen one fix go through for one use case of one piece of code >>> that repeatedly uses potentially misaligned int[] arrays for bitmasks. >>>=20 >>=20 >> Can we really not just change the lock asm to use 32-bit accesses for >> set_bit(), etc? Sure, it will fail if the bit index is greater than >> 2^32, but that seems nuts. >>=20 >> (Why the *hell* do the bitops use long anyway? They're *bit masks* >> for crying out loud. As in, users generally want to operate on fixed >> numbers of bits.) >=20 > We are working on a separate patch set to fix all split lock issues > in atomic bitops. Per Peter Anvin and Tony Luck suggestions: > 1. Still keep the byte optimization if nr is constant. No split lock. > 2. If type of *addr is unsigned long, do quadword atomic instruction > on addr. No split lock. > 3. If type of *addr is unsigned int, do word atomic instruction > on addr. No split lock. > 4. Otherwise, re-calculate addr to point the 32-bit address which contains= > the bit and operate on the bit. No split lock. >=20 > Only small percentage of atomic bitops calls are in case 4 (e.g. 3% > for set_bit()) which need a few extra instructions to re-calculate > address but can avoid big split lock overhead. >=20 > To get real type of *addr instead of type cast type "unsigned long", > the atomic bitops APIs are changed to macros from functions. This change > need to touch all architectures. >=20 Isn=E2=80=99t the kernel full of casts to long* to match the signature? Doi= ng this based on type seems silly to me. I think it=E2=80=99s better to just= to a 32-bit operation unconditionally and to try to optimize it using b*l w= hen safe.=