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[91.79.162.105]) by smtp.googlemail.com with ESMTPSA id d6sm4553300ljc.23.2020.07.14.02.36.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 14 Jul 2020 02:36:52 -0700 (PDT) Subject: Re: [PATCH v4] clk: tegra: pll: Improve PLLM enable-state detection To: Jon Hunter , Thierry Reding , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20200709172057.13951-1-digetx@gmail.com> <93106a4c-b0fb-3bbf-49cb-bfe348b1ffc7@nvidia.com> From: Dmitry Osipenko Message-ID: <4abe7959-3c69-7b05-e9af-565957bafbcd@gmail.com> Date: Tue, 14 Jul 2020 12:36:51 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <93106a4c-b0fb-3bbf-49cb-bfe348b1ffc7@nvidia.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 14.07.2020 11:20, Jon Hunter пишет: > > On 09/07/2020 18:20, Dmitry Osipenko wrote: >> Power Management Controller (PMC) can override the PLLM clock settings, >> including the enable-state. Although PMC could only act as a second level >> gate, meaning that PLLM needs to be enabled by the Clock and Reset >> Controller (CaR) anyways if we want it to be enabled. Hence, when PLLM is >> overridden by PMC, it needs to be enabled by CaR and ungated by PMC in >> order to be functional. Please note that this patch doesn't fix any known >> problem, and thus, it's merely a minor improvement. >> >> Link: https://lore.kernel.org/linux-arm-kernel/20191210120909.GA2703785@ulmo/T/ >> Signed-off-by: Dmitry Osipenko >> --- >> >> Changelog: >> >> v4: - Renamed pllm_pmc_clk_enabled() to pllm_clk_is_gated_by_pmc() as >> it was suggested by Jon Hunter in the review comment to v3. >> >> v3: - Dropped unintended code change that was accidentally added to v2. >> >> v2: - Added clarifying comment to the code. >> >> - Prettified the code. >> >> drivers/clk/tegra/clk-pll.c | 20 +++++++++++++++----- >> 1 file changed, 15 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c >> index b2d39a66f0fa..ff13b371e176 100644 >> --- a/drivers/clk/tegra/clk-pll.c >> +++ b/drivers/clk/tegra/clk-pll.c >> @@ -327,16 +327,26 @@ int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll) >> return clk_pll_wait_for_lock(pll); >> } >> >> +static bool pllm_clk_is_gated_by_pmc(struct tegra_clk_pll *pll) >> +{ >> + u32 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); >> + >> + return (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) && >> + !(val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE); >> +} >> + >> static int clk_pll_is_enabled(struct clk_hw *hw) >> { >> struct tegra_clk_pll *pll = to_clk_pll(hw); >> u32 val; >> >> - if (pll->params->flags & TEGRA_PLLM) { >> - val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); >> - if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) >> - return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0; >> - } >> + /* >> + * Power Management Controller (PMC) can override the PLLM clock >> + * settings, including the enable-state. The PLLM is enabled when >> + * PLLM's CaR state is ON and when PLLM isn't gated by PMC. >> + */ >> + if ((pll->params->flags & TEGRA_PLLM) && pllm_clk_is_gated_by_pmc(pll)) >> + return 0; >> >> val = pll_readl_base(pll); > > > Thanks! This looks good to me. However, I just want to do a bit of > testing on Tegra124 (hopefully this week). Okay, thank you :)