From: Ludovic BARRE <ludovic.barre@st.com>
To: Linus Walleij <linus.walleij@linaro.org>,
Rob Herring <robh+dt@kernel.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@st.com>,
<linux-gpio@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/2] pinctrl: stm32: add syscfg mask parameter
Date: Tue, 17 Jul 2018 15:11:22 +0200 [thread overview]
Message-ID: <4acc415d-f162-67a2-57d6-0a7defda434f@st.com> (raw)
In-Reply-To: <1531821387-29845-3-git-send-email-ludovic.Barre@st.com>
Hi
add Rob, I forgotten rob's mail.
On 07/17/2018 11:56 AM, Ludovic Barre wrote:
> From: Ludovic Barre <ludovic.barre@st.com>
>
> This patch adds mask parameter to define IRQ mux field.
> This field could vary depend of IRQ mux selection register.
> To avoid backward compatibility, the drivers set
> the legacy value by default.
>
> Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
> ---
> drivers/pinctrl/stm32/pinctrl-stm32.c | 16 ++++++++++++++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
> index dfed609..f756232 100644
> --- a/drivers/pinctrl/stm32/pinctrl-stm32.c
> +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
> @@ -46,6 +46,8 @@
> #define STM32_GPIO_PINS_PER_BANK 16
> #define STM32_GPIO_IRQ_LINE 16
>
> +#define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
> +
> #define gpio_range_to_bank(chip) \
> container_of(chip, struct stm32_gpio_bank, range)
>
> @@ -1033,6 +1035,7 @@ static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
> struct device *dev = &pdev->dev;
> struct regmap *rm;
> int offset, ret, i;
> + int mask, mask_width;
>
> parent = of_irq_find_parent(np);
> if (!parent)
> @@ -1052,12 +1055,21 @@ static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
> if (ret)
> return ret;
>
> + ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
> + if (ret)
> + mask = SYSCFG_IRQMUX_MASK;
> +
> + mask_width = fls(mask);
> +
> for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
> struct reg_field mux;
>
> mux.reg = offset + (i / 4) * 4;
> - mux.lsb = (i % 4) * 4;
> - mux.msb = mux.lsb + 3;
> + mux.lsb = (i % 4) * mask_width;
> + mux.msb = mux.lsb + mask_width - 1;
> +
> + dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
> + i, mux.reg, mux.lsb, mux.msb);
>
> pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
> if (IS_ERR(pctl->irqmux[i]))
>
next prev parent reply other threads:[~2018-07-17 13:11 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-17 9:56 [PATCH 0/2] add syscfg mask parameter Ludovic Barre
2018-07-17 9:56 ` [PATCH 1/2] dt-bindings: pinctrl: " Ludovic Barre
2018-07-17 13:09 ` Ludovic BARRE
2018-07-17 13:29 ` Alexandre Torgue
2018-07-29 20:14 ` Linus Walleij
2018-07-17 9:56 ` [PATCH 2/2] pinctrl: stm32: " Ludovic Barre
2018-07-17 13:11 ` Ludovic BARRE [this message]
2018-07-17 13:30 ` Alexandre Torgue
2018-07-29 20:15 ` Linus Walleij
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