[PATCH 1/2] riscv: Fix building error in entry.S when CONFIG_RISCV_M_MODE is enabled

[PATCH 1/2] riscv: Fix building error in entry.S when CONFIG_RISCV_M_MODE is enabled

[Greentime Hu]

arch/riscv/kernel/entry.S: Assembler messages:
arch/riscv/kernel/entry.S:106: Error: illegal operands `andi a0,s1,0x00001800'

This building error is because of the SR_MPP value is too large to be used
as an immediate value for andi. To fix this issue I use li to set the
immediate value to t0, then it can use t0 and s1 to do and operation.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
---
 arch/riscv/kernel/entry.S | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 6ed579fc1073..000984695cd6 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -99,7 +99,8 @@ _save_context:
 
 #ifdef CONFIG_CONTEXT_TRACKING
 	/* If previous state is in user mode, call context_tracking_user_exit. */
-	andi a0, s1, SR_SPP
+	li t0, SR_PP
+	and a0, s1, t0
 	bnez a0, skip_context_tracking
 	call context_tracking_user_exit
 
-- 
2.27.0

[PATCH 2/2] riscv: Simplify the checking for SR_PP

[Greentime Hu]

This patch simplifies the checking for SR_MPP and SR_SPP. It uses SR_PP in the
code flow for both m-mode and s-mode then we can remove the ifdef here.

Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
---
 arch/riscv/kernel/entry.S | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 000984695cd6..597beae0d238 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -210,13 +210,8 @@ ret_from_syscall_rejected:
 ret_from_exception:
 	REG_L s0, PT_STATUS(sp)
 	csrc CSR_STATUS, SR_IE
-#ifdef CONFIG_RISCV_M_MODE
-	/* the MPP value is too large to be used as an immediate arg for addi */
-	li t0, SR_MPP
+	li t0, SR_PP
 	and s0, s0, t0
-#else
-	andi s0, s0, SR_SPP
-#endif
 	bnez s0, resume_kernel
 
 resume_userspace:
-- 
2.27.0

Re: [PATCH 1/2] riscv: Fix building error in entry.S when CONFIG_RISCV_M_MODE is enabled

[Palmer Dabbelt]

On Mon, 13 Jul 2020 01:32:15 PDT (-0700), greentime.hu@sifive.com wrote:
> arch/riscv/kernel/entry.S: Assembler messages:
> arch/riscv/kernel/entry.S:106: Error: illegal operands `andi a0,s1,0x00001800'
>
> This building error is because of the SR_MPP value is too large to be used
> as an immediate value for andi. To fix this issue I use li to set the
> immediate value to t0, then it can use t0 and s1 to do and operation.

Thanks.  I guess I must have something wrong with my build tests, as it's
supposed to be building the NOMMU stuff.  I was just about to fix this up in
the patch, looks like I also lost my own Signed-off-by so I have to ammend it
anyway.

>
> Reported-by: kernel test robot <lkp@intel.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> ---
>  arch/riscv/kernel/entry.S | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> index 6ed579fc1073..000984695cd6 100644
> --- a/arch/riscv/kernel/entry.S
> +++ b/arch/riscv/kernel/entry.S
> @@ -99,7 +99,8 @@ _save_context:
>
>  #ifdef CONFIG_CONTEXT_TRACKING
>  	/* If previous state is in user mode, call context_tracking_user_exit. */
> -	andi a0, s1, SR_SPP
> +	li t0, SR_PP
> +	and a0, s1, t0
>  	bnez a0, skip_context_tracking
>  	call context_tracking_user_exit

Re: [PATCH 1/2] riscv: Fix building error in entry.S when CONFIG_RISCV_M_MODE is enabled

[Palmer Dabbelt]

On Mon, 13 Jul 2020 01:32:15 PDT (-0700), greentime.hu@sifive.com wrote:
> arch/riscv/kernel/entry.S: Assembler messages:
> arch/riscv/kernel/entry.S:106: Error: illegal operands `andi a0,s1,0x00001800'
>
> This building error is because of the SR_MPP value is too large to be used
> as an immediate value for andi. To fix this issue I use li to set the
> immediate value to t0, then it can use t0 and s1 to do and operation.
>
> Reported-by: kernel test robot <lkp@intel.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> ---
>  arch/riscv/kernel/entry.S | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> index 6ed579fc1073..000984695cd6 100644
> --- a/arch/riscv/kernel/entry.S
> +++ b/arch/riscv/kernel/entry.S
> @@ -99,7 +99,8 @@ _save_context:
>
>  #ifdef CONFIG_CONTEXT_TRACKING
>  	/* If previous state is in user mode, call context_tracking_user_exit. */
> -	andi a0, s1, SR_SPP
> +	li t0, SR_PP
> +	and a0, s1, t0
>  	bnez a0, skip_context_tracking
>  	call context_tracking_user_exit

Looks like this one already got fixed, I guess I saw the build report go by and
fixed it?  I don't remember if I actually pulled this in, but I ended up with a
3-register andi so I guess I didn't do it that well.

I'm not sure why my build test aren't catching the M-mode stuff, as the
defconfigs are in the list.  I'll go take a look...

Re: [PATCH 2/2] riscv: Simplify the checking for SR_PP

[Palmer Dabbelt]

On Mon, 13 Jul 2020 01:32:16 PDT (-0700), greentime.hu@sifive.com wrote:
> This patch simplifies the checking for SR_MPP and SR_SPP. It uses SR_PP in the
> code flow for both m-mode and s-mode then we can remove the ifdef here.
>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> ---
>  arch/riscv/kernel/entry.S | 7 +------
>  1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> index 000984695cd6..597beae0d238 100644
> --- a/arch/riscv/kernel/entry.S
> +++ b/arch/riscv/kernel/entry.S
> @@ -210,13 +210,8 @@ ret_from_syscall_rejected:
>  ret_from_exception:
>  	REG_L s0, PT_STATUS(sp)
>  	csrc CSR_STATUS, SR_IE
> -#ifdef CONFIG_RISCV_M_MODE
> -	/* the MPP value is too large to be used as an immediate arg for addi */
> -	li t0, SR_MPP
> +	li t0, SR_PP
>  	and s0, s0, t0
> -#else
> -	andi s0, s0, SR_SPP
> -#endif
>  	bnez s0, resume_kernel
>
>  resume_userspace:

This one is actually on a fairly fast path, so I can buy it's worth saving the
cycle.