From: John Garry <john.garry@huawei.com>
To: Andrew Kilroy <andrew.kilroy@arm.com>,
<linux-kernel@vger.kernel.org>,
<linux-perf-users@vger.kernel.org>, <acme@kernel.org>
Cc: Will Deacon <will@kernel.org>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Leo Yan <leo.yan@linaro.org>, Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@redhat.com>,
"Namhyung Kim" <namhyung@kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Zhangshaokun <zhangshaokun@hisilicon.com>
Subject: Re: [PATCH v2 1/2] perf vendor events: For the Arm Neoverse N2
Date: Fri, 10 Dec 2021 13:21:41 +0000 [thread overview]
Message-ID: <4c375d34-bf20-496d-22fc-aed8597126e2@huawei.com> (raw)
In-Reply-To: <20211210123706.7490-2-andrew.kilroy@arm.com>
On 10/12/2021 12:37, Andrew Kilroy wrote:
> Updates the common and microarch json file to add counters available in
> the Arm Neoverse N2 chip, but should also apply to other ArmV8 and ArmV9
> cpus. Specified in ArmV8 architecture reference manual
>
> https://developer.arm.com/documentation/ddi0487/gb/?lang=en
>
> Some of the counters added to armv8-common-and-microarch.json are
> specified in the ArmV9 architecture reference manual supplement
> (issue A.a):
>
> https://developer.arm.com/documentation/ddi0608/aa
>
> The additional ArmV9 counters are
>
> TRB_WRAP
> TRCEXTOUT0
> TRCEXTOUT1
> TRCEXTOUT2
> TRCEXTOUT3
> CTI_TRIGOUT4
> CTI_TRIGOUT5
> CTI_TRIGOUT6
> CTI_TRIGOUT7
>
> This patch also adds files in pmu-events/arch/arm64/arm/neoverse-n2 for
> perf list to output the counter names in categories.
>
> Counters on the Neoverse N2 are stated in its reference manual:
>
> https://developer.arm.com/documentation/102099/0000
>
> Signed-off-by: Andrew Kilroy<andrew.kilroy@arm.com>
> ---
> .../arch/arm64/arm/neoverse-n2/branch.json | 8 +
> .../arch/arm64/arm/neoverse-n2/bus.json | 20 ++
> .../arch/arm64/arm/neoverse-n2/cache.json | 155 ++++++++++++++
> .../arch/arm64/arm/neoverse-n2/exception.json | 47 +++++
> .../arm64/arm/neoverse-n2/instruction.json | 143 +++++++++++++
> .../arch/arm64/arm/neoverse-n2/memory.json | 38 ++++
> .../arch/arm64/arm/neoverse-n2/other.json | 5 +
> .../arch/arm64/arm/neoverse-n2/pipeline.json | 23 ++
> .../arch/arm64/arm/neoverse-n2/spe.json | 14 ++
> .../arch/arm64/arm/neoverse-n2/trace.json | 29 +++
> .../arm64/armv8-common-and-microarch.json | 198 ++++++++++++++++++
> tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
> 12 files changed, 681 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/other.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/spe.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/trace.json
>
> diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/branch.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/branch.json
This looks ok,
Reviewed-by: John Garry <john.garry@huawei.com>
BTW, I was looking at adding perf tool --topdown support for arm64. This
will require L1 metricgroup support per core - see what I did here for
our hisilicon platform already:
[0]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/metrics.json
I would like to add support for more cores. Generally the arm common
events match up to the definitions here:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/perf/Documentation/perf-stat.txt#n400
Apart from frontend_bound - would you have an equivalent metric
expression for this for these Neoverse cores?
[0] Note that I think that the divisor in the metric expressions is max
uops that the core can deal with.
Thanks,
John
next prev parent reply other threads:[~2021-12-10 13:22 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-10 12:37 [PATCH v2 0/2] perf vendor events: Arm Neoverse N2 Andrew Kilroy
2021-12-10 12:37 ` [PATCH v2 1/2] perf vendor events: For the " Andrew Kilroy
2021-12-10 13:21 ` John Garry [this message]
2021-12-14 18:42 ` [RFC PATCH 0/1] topdown with metrics Andrew Kilroy
2021-12-14 18:42 ` [RFC PATCH 1/1] perf arm64: Implement --topdown " Andrew Kilroy
2021-12-14 20:32 ` Ian Rogers
2021-12-15 10:38 ` James Clark
2021-12-15 10:52 ` John Garry
2021-12-15 12:38 ` Andrew Kilroy
2021-12-15 12:53 ` John Garry
2022-01-06 16:33 ` Andrew Kilroy
2022-01-06 18:24 ` John Garry
2022-01-11 15:07 ` [RFC PATCH v2 0/5] topdown " Andrew Kilroy
2022-01-11 15:07 ` [RFC PATCH v2 1/5] perf stat: Implement --topdown " Andrew Kilroy
2022-01-28 13:44 ` John Garry
2022-01-11 15:07 ` [RFC PATCH v2 2/5] perf stat: Topdown kernel events setup function Andrew Kilroy
2022-01-11 15:07 ` [RFC PATCH v2 3/5] perf stat: Topdown json metrics " Andrew Kilroy
2022-01-11 15:07 ` [RFC PATCH v2 4/5] perf stat: Detect if topdown kernel events supported Andrew Kilroy
2022-01-11 15:07 ` [RFC PATCH v2 5/5] perf stat: Ensure only topdown kernel events used on x86 Andrew Kilroy
2022-01-20 9:26 ` [RFC PATCH v2 0/5] topdown with metrics John Garry
2022-01-20 16:22 ` Al Grant
2022-01-27 11:42 ` Andrew Kilroy
2022-02-08 15:58 ` Andrew Kilroy
2021-12-20 17:21 ` [RFC PATCH 1/1] perf arm64: Implement --topdown " Andrew Kilroy
2021-12-21 14:03 ` Andi Kleen
2022-01-27 11:11 ` Andrew Kilroy
2021-12-17 10:19 ` John Garry
2021-12-21 14:31 ` Andrew Kilroy
2022-01-05 16:58 ` Andrew Kilroy
2022-01-28 18:00 ` John Garry
2021-12-10 12:37 ` [PATCH v2 2/2] perf vendor events: Rename arm64 arch std event files Andrew Kilroy
2021-12-10 13:46 ` John Garry
2021-12-10 19:01 ` Arnaldo Carvalho de Melo
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