From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753299AbdAZJKM (ORCPT ); Thu, 26 Jan 2017 04:10:12 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:45965 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753107AbdAZJGK (ORCPT ); Thu, 26 Jan 2017 04:06:10 -0500 From: Maxime Ripard To: Chen-Yu Tsai , Maxime Ripard , Ulf Hansson Cc: Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Andre Przywara Subject: [PATCH v4 12/13] arm64: allwinner: a64: add UART1 pin nodes Date: Thu, 26 Jan 2017 10:06:05 +0100 Message-Id: <4c3bab1dc2b6d900b4bab76181a08eae8a27a785.1485421557.git-series.maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andre Przywara On many boards UART1 connects to a Bluetooth chip, so add the pinctrl nodes for the only pins providing access to that UART. That includes those pins for hardware flow control (RTS/CTS). Signed-off-by: Andre Przywara Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+), 0 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index cb3e0cf2191a..d27b17f807d0 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -276,6 +276,16 @@ pins = "PB8", "PB9"; function = "uart0"; }; + + uart1_pins: uart1_pins { + pins = "PG6", "PG7"; + function = "uart1"; + }; + + uart1_rts_cts_pins: uart1_rts_cts_pins { + pins = "PG8", "PG9"; + function = "uart1"; + }; }; uart0: serial@1c28000 { -- git-series 0.8.11