* [PATCH 1/7] Revert "ARM: mediatek: add MT7623a smp bringup code"
@ 2019-01-29 4:28 Ryder Lee
2019-01-29 4:31 ` [PATCH 2/7] dt-bindings: arm: mediatek: remove unused "mediatek,mt7623a" Ryder Lee
` (6 more replies)
0 siblings, 7 replies; 14+ messages in thread
From: Ryder Lee @ 2019-01-29 4:28 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, Sean Wang, Weijie Gao, Roy Luo, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Ryder Lee
This reverts commit 3b99ab7deca1e5f4229b4bdecd005d71e22cfc60.
The compatible "mediatek,mt7623a" is useless, so remove it.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
arch/arm/mach-mediatek/mediatek.c | 2 --
arch/arm/mach-mediatek/platsmp.c | 1 -
2 files changed, 3 deletions(-)
diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
index 6910b4e..c3cf215 100644
--- a/arch/arm/mach-mediatek/mediatek.c
+++ b/arch/arm/mach-mediatek/mediatek.c
@@ -30,7 +30,6 @@ static void __init mediatek_timer_init(void)
if (of_machine_is_compatible("mediatek,mt6589") ||
of_machine_is_compatible("mediatek,mt7623") ||
- of_machine_is_compatible("mediatek,mt7623a") ||
of_machine_is_compatible("mediatek,mt8135") ||
of_machine_is_compatible("mediatek,mt8127")) {
/* turn on GPT6 which ungates arch timer clocks */
@@ -50,7 +49,6 @@ static void __init mediatek_timer_init(void)
"mediatek,mt6589",
"mediatek,mt6592",
"mediatek,mt7623",
- "mediatek,mt7623a",
"mediatek,mt8127",
"mediatek,mt8135",
NULL,
diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c
index 6882ff0..51e8556 100644
--- a/arch/arm/mach-mediatek/platsmp.c
+++ b/arch/arm/mach-mediatek/platsmp.c
@@ -60,7 +60,6 @@ struct mtk_smp_boot_info {
static const struct of_device_id mtk_smp_boot_infos[] __initconst = {
{ .compatible = "mediatek,mt6589", .data = &mtk_mt6589_boot },
{ .compatible = "mediatek,mt7623", .data = &mtk_mt7623_boot },
- { .compatible = "mediatek,mt7623a", .data = &mtk_mt7623_boot },
{},
};
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/7] dt-bindings: arm: mediatek: remove unused "mediatek,mt7623a"
2019-01-29 4:28 [PATCH 1/7] Revert "ARM: mediatek: add MT7623a smp bringup code" Ryder Lee
@ 2019-01-29 4:31 ` Ryder Lee
2019-01-29 4:31 ` [PATCH 3/7] dt-bindings: arm: mediatek: add support for MT7622 BPI-R64 and MT7629 RFB Ryder Lee
` (5 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Ryder Lee @ 2019-01-29 4:31 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, Sean Wang, Weijie Gao, Roy Luo, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Ryder Lee
As we fallback to use "mediatek,mt7623" for MT7623a, remove unused
root node property "mediatek,mt7623a" in the document.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
Documentation/devicetree/bindings/arm/mediatek.txt | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
index 8f260e5..a3d1b4f 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -15,8 +15,7 @@ compatible: Must contain one of
"mediatek,mt6795"
"mediatek,mt6797"
"mediatek,mt7622"
- "mediatek,mt7623" which is referred to MT7623N SoC
- "mediatek,mt7623a"
+ "mediatek,mt7623"
"mediatek,mt8127"
"mediatek,mt8135"
"mediatek,mt8173"
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/7] dt-bindings: arm: mediatek: add support for MT7622 BPI-R64 and MT7629 RFB
2019-01-29 4:28 [PATCH 1/7] Revert "ARM: mediatek: add MT7623a smp bringup code" Ryder Lee
2019-01-29 4:31 ` [PATCH 2/7] dt-bindings: arm: mediatek: remove unused "mediatek,mt7623a" Ryder Lee
@ 2019-01-29 4:31 ` Ryder Lee
2019-02-13 20:12 ` Rob Herring
2019-01-29 4:31 ` [PATCH 4/7] dt-bindings: mediatek: update bindings for MT7629 SoC Ryder Lee
` (4 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Ryder Lee @ 2019-01-29 4:31 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, Sean Wang, Weijie Gao, Roy Luo, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Ryder Lee
Update binding document for MT7622 BPI-R64 and MT7629 reference board.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
Documentation/devicetree/bindings/arm/mediatek.txt | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
index a3d1b4f..3ebcc9e 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -16,6 +16,7 @@ compatible: Must contain one of
"mediatek,mt6797"
"mediatek,mt7622"
"mediatek,mt7623"
+ "mediatek,mt7629"
"mediatek,mt8127"
"mediatek,mt8135"
"mediatek,mt8173"
@@ -56,6 +57,9 @@ Supported boards:
- Reference board variant 1 for MT7622:
Required root node properties:
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
+- Bananapi BPI-R64 for MT7622:
+ Required root node properties:
+ - compatible = "bananapi,bpi-r64", "mediatek,mt7622";
- Reference board for MT7623a with eMMC:
Required root node properties:
- compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623";
@@ -67,6 +71,9 @@ Supported boards:
- compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623";
- Bananapi BPI-R2 board:
- compatible = "bananapi,bpi-r2", "mediatek,mt7623";
+- Reference board for MT7629:
+ Required root node properties:
+ - compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
- MTK mt8127 tablet moose EVB:
Required root node properties:
- compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/7] dt-bindings: mediatek: update bindings for MT7629 SoC
2019-01-29 4:28 [PATCH 1/7] Revert "ARM: mediatek: add MT7623a smp bringup code" Ryder Lee
2019-01-29 4:31 ` [PATCH 2/7] dt-bindings: arm: mediatek: remove unused "mediatek,mt7623a" Ryder Lee
2019-01-29 4:31 ` [PATCH 3/7] dt-bindings: arm: mediatek: add support for MT7622 BPI-R64 and MT7629 RFB Ryder Lee
@ 2019-01-29 4:31 ` Ryder Lee
2019-02-08 12:28 ` Matthias Brugger
2019-01-29 4:31 ` [PATCH 5/7] dt-bindings: interrupt-controller: update bindings for MT7623 Ryder Lee
` (3 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Ryder Lee @ 2019-01-29 4:31 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, Sean Wang, Weijie Gao, Roy Luo, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Ryder Lee
This updates bindings for MT7629 SoC, which includes very basic items
such as system timer, UART, sysirq and scpsys unit.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
.../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt | 5 +++--
Documentation/devicetree/bindings/serial/mtk-uart.txt | 3 ++-
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt | 5 +++--
Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 7 ++++---
4 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index 33a98eb..8da481c 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -1,6 +1,6 @@
-+Mediatek MT65xx/MT67xx/MT81xx sysirq
+MediaTek sysirq
-Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
+MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
interrupt.
Required properties:
@@ -9,6 +9,7 @@ Required properties:
"mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
"mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
"mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
+ "mediatek,mt7629-sysirq", "mediatek,mt6577-sysirq": for MT7629
"mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
"mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
"mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 742cb47..4910f63 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -1,4 +1,4 @@
-* Mediatek Universal Asynchronous Receiver/Transmitter (UART)
+* MediaTek Universal Asynchronous Receiver/Transmitter (UART)
Required properties:
- compatible should contain:
@@ -13,6 +13,7 @@ Required properties:
* "mediatek,mt6797-uart" for MT6797 compatible UARTS
* "mediatek,mt7622-uart" for MT7622 compatible UARTS
* "mediatek,mt7623-uart" for MT7623 compatible UARTS
+ * "mediatek,mt7629-uart" for MT7629 compatible UARTS
* "mediatek,mt8127-uart" for MT8127 compatible UARTS
* "mediatek,mt8135-uart" for MT8135 compatible UARTS
* "mediatek,mt8173-uart" for MT8173 compatible UARTS
diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index d6fe16f..876693a 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -23,6 +23,7 @@ Required properties:
- "mediatek,mt7622-scpsys"
- "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC
- "mediatek,mt7623a-scpsys": For MT7623A SoC
+ - "mediatek,mt7629-scpsys", "mediatek,mt7622-scpsys": For MT7629 SoC
- "mediatek,mt8173-scpsys"
- #power-domain-cells: Must be 1
- reg: Address range of the SCPSYS unit
@@ -33,8 +34,8 @@ Required properties:
Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
Required clocks for MT6797: "mm", "mfg", "vdec"
- Required clocks for MT7622: "hif_sel"
- Required clocks for MT7622A: "ethif"
+ Required clocks for MT7622 or MT7629: "hif_sel"
+ Required clocks for MT7623A: "ethif"
Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
Optional properties:
diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
index 18d4d01..12b6d06 100644
--- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
+++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
@@ -1,7 +1,7 @@
-Mediatek Timers
+MediaTek Timers
---------------
-Mediatek SoCs have two different timers on different platforms,
+MediaTek SoCs have two different timers on different platforms,
- GPT (General Purpose Timer)
- SYST (System Timer)
@@ -17,7 +17,8 @@ Required properties:
* "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
* "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
* "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)
- * "mediatek,mt6765-timer" for MT6765 compatible timers (SYST)
+ * "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)
+ * "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST)
- reg: Should contain location and length for timer register.
- clocks: Should contain system clock.
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 5/7] dt-bindings: interrupt-controller: update bindings for MT7623
2019-01-29 4:28 [PATCH 1/7] Revert "ARM: mediatek: add MT7623a smp bringup code" Ryder Lee
` (2 preceding siblings ...)
2019-01-29 4:31 ` [PATCH 4/7] dt-bindings: mediatek: update bindings for MT7629 SoC Ryder Lee
@ 2019-01-29 4:31 ` Ryder Lee
2019-02-07 17:11 ` Matthias Brugger
2019-01-29 4:31 ` [PATCH 6/7] arm: mediatek: add MT7629 smp bring up code Ryder Lee
` (2 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Ryder Lee @ 2019-01-29 4:31 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, Sean Wang, Weijie Gao, Roy Luo, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Ryder Lee
This adds missing bindings for MT7623 sysirq.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
.../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index 8da481c..e8b3688 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -9,6 +9,7 @@ Required properties:
"mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
"mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
"mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
+ "mediatek,mt7623-sysirq", "mediatek,mt6577-sysirq": for MT7623
"mediatek,mt7629-sysirq", "mediatek,mt6577-sysirq": for MT7629
"mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
"mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 6/7] arm: mediatek: add MT7629 smp bring up code
2019-01-29 4:28 [PATCH 1/7] Revert "ARM: mediatek: add MT7623a smp bringup code" Ryder Lee
` (3 preceding siblings ...)
2019-01-29 4:31 ` [PATCH 5/7] dt-bindings: interrupt-controller: update bindings for MT7623 Ryder Lee
@ 2019-01-29 4:31 ` Ryder Lee
2019-01-29 4:31 ` [PATCH 7/7] arm: dts: mediatek: add basic support for MT7629 SoC Ryder Lee
2019-02-07 16:47 ` [PATCH 1/7] Revert "ARM: mediatek: add MT7623a smp bringup code" Matthias Brugger
6 siblings, 0 replies; 14+ messages in thread
From: Ryder Lee @ 2019-01-29 4:31 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, Sean Wang, Weijie Gao, Roy Luo, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Ryder Lee
Add support for booting secondary CPUs on MT7629.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
arch/arm/mach-mediatek/Kconfig | 4 ++++
arch/arm/mach-mediatek/mediatek.c | 1 +
arch/arm/mach-mediatek/platsmp.c | 1 +
3 files changed, 6 insertions(+)
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 91cc461..11ed264 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -26,6 +26,10 @@ config MACH_MT7623
bool "MediaTek MT7623 SoCs support"
default ARCH_MEDIATEK
+config MACH_MT7629
+ bool "MediaTek MT7629 SoCs support"
+ default ARCH_MEDIATEK
+
config MACH_MT8127
bool "MediaTek MT8127 SoCs support"
default ARCH_MEDIATEK
diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
index c3cf215..b6a81ba 100644
--- a/arch/arm/mach-mediatek/mediatek.c
+++ b/arch/arm/mach-mediatek/mediatek.c
@@ -49,6 +49,7 @@ static void __init mediatek_timer_init(void)
"mediatek,mt6589",
"mediatek,mt6592",
"mediatek,mt7623",
+ "mediatek,mt7629",
"mediatek,mt8127",
"mediatek,mt8135",
NULL,
diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c
index 51e8556..c9d7c04 100644
--- a/arch/arm/mach-mediatek/platsmp.c
+++ b/arch/arm/mach-mediatek/platsmp.c
@@ -60,6 +60,7 @@ struct mtk_smp_boot_info {
static const struct of_device_id mtk_smp_boot_infos[] __initconst = {
{ .compatible = "mediatek,mt6589", .data = &mtk_mt6589_boot },
{ .compatible = "mediatek,mt7623", .data = &mtk_mt7623_boot },
+ { .compatible = "mediatek,mt7629", .data = &mtk_mt7623_boot },
{},
};
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 7/7] arm: dts: mediatek: add basic support for MT7629 SoC
2019-01-29 4:28 [PATCH 1/7] Revert "ARM: mediatek: add MT7623a smp bringup code" Ryder Lee
` (4 preceding siblings ...)
2019-01-29 4:31 ` [PATCH 6/7] arm: mediatek: add MT7629 smp bring up code Ryder Lee
@ 2019-01-29 4:31 ` Ryder Lee
2019-02-08 12:30 ` Matthias Brugger
2019-02-25 14:37 ` Rob Herring
2019-02-07 16:47 ` [PATCH 1/7] Revert "ARM: mediatek: add MT7623a smp bringup code" Matthias Brugger
6 siblings, 2 replies; 14+ messages in thread
From: Ryder Lee @ 2019-01-29 4:31 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, Sean Wang, Weijie Gao, Roy Luo, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Ryder Lee
This adds basic support for MT7629 reference board.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
The I2C node depends on https://patchwork.kernel.org/patch/10772837/
The PCIe node depends on https://patchwork.kernel.org/patch/10773637/
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/mt7629-rfb.dts | 234 +++++++++++++++++
arch/arm/boot/dts/mt7629.dtsi | 416 ++++++++++++++++++++++++++++++
include/dt-bindings/reset/mt7629-resets.h | 71 +++++
4 files changed, 722 insertions(+)
create mode 100644 arch/arm/boot/dts/mt7629-rfb.dts
create mode 100644 arch/arm/boot/dts/mt7629.dtsi
create mode 100644 include/dt-bindings/reset/mt7629-resets.h
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index bd40148..a5a6d9f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1231,6 +1231,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623a-rfb-nand.dtb \
mt7623n-rfb-emmc.dtb \
mt7623n-bananapi-bpi-r2.dtb \
+ mt7629-rfb.dtb \
mt8127-moose.dtb \
mt8135-evbp1.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
diff --git a/arch/arm/boot/dts/mt7629-rfb.dts b/arch/arm/boot/dts/mt7629-rfb.dts
new file mode 100644
index 0000000..0878a14
--- /dev/null
+++ b/arch/arm/boot/dts/mt7629-rfb.dts
@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include "mt7629.dtsi"
+
+/ {
+ model = "MediaTek MT7629 reference board";
+ compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "earlycon=uart8250,mmio32,0x11002000";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "factory";
+ linux,code = <KEY_RESTART>;
+ gpios = <&pio 60 GPIO_ACTIVE_LOW>;
+ };
+
+ wps {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&pio 58 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x10000000>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&i2c {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_pins>;
+ status = "okay";
+};
+
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&qspi_pins>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@00000 {
+ label = "Bootloader";
+ reg = <0x00000 0x0060000>;
+ };
+
+ partition@60000 {
+ label = "Config";
+ reg = <0x60000 0x0010000>;
+ };
+
+ partition@70000 {
+ label = "Factory";
+ reg = <0x70000 0x0040000>;
+ };
+
+ partition@b0000 {
+ label = "Kernel";
+ reg = <0xb0000 0xb50000>;
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pins>;
+ status = "okay";
+
+ pcie@1,0 {
+ status = "okay";
+ };
+};
+
+&pio {
+ eth_pins: eth-pins {
+ mux {
+ function = "eth";
+ groups = "mdc_mdio";
+ };
+ };
+
+ ephy_leds_pins: ephy-leds-pins {
+ mux {
+ function = "led";
+ groups = "gphy_leds_0", "ephy_leds";
+ };
+ };
+
+ i2c_pins: i2c-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c_0";
+ };
+
+ conf {
+ pins = "I2C_SDA", "I2C_SCL";
+ drive-strength = <4>;
+ bias-disable;
+ };
+ };
+
+ pcie_pins: pcie-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_clkreq",
+ "pcie_pereset",
+ "pcie_wake";
+ };
+ };
+
+ pwm_pins: pwm-pins {
+ mux {
+ function = "pwm";
+ groups = "pwm_0";
+ };
+ };
+
+ /* Serial NAND is shared pin with SPI-NOR */
+ serial_nand_pins: serial-nand-pins {
+ mux {
+ function = "flash";
+ groups = "snfi";
+ };
+ };
+
+ spi_pins: spi-pins {
+ mux {
+ function = "spi";
+ groups = "spi_0";
+ };
+ };
+
+ /* SPI-NOR is shared pin with serial NAND */
+ qspi_pins: qspi-pins {
+ mux {
+ function = "flash";
+ groups = "spi_nor";
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ mux {
+ function = "uart";
+ groups = "uart0_txd_rxd" ;
+ };
+ };
+
+ uart1_pins: uart1-pins {
+ mux {
+ function = "uart";
+ groups = "uart1_0_tx_rx" ;
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ mux {
+ function = "uart";
+ groups = "uart2_0_txd_rxd" ;
+ };
+ };
+
+ watchdog_pins: watchdog-pins {
+ mux {
+ function = "watchdog";
+ groups = "watchdog";
+ };
+ };
+};
+
+&spi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_pins>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&ssusb {
+ vusb33-supply = <®_3p3v>;
+ vbus-supply = <®_5v>;
+ status = "okay";
+};
+
+&u3phy1 {
+ status = "okay";
+};
+
+&watchdog {
+ pinctrl-names = "default";
+ pinctrl-0 = <&watchdog_pins>;
+ status = "okay";
+};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi
new file mode 100644
index 0000000..2b4410a
--- /dev/null
+++ b/arch/arm/boot/dts/mt7629.dtsi
@@ -0,0 +1,416 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ *
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mt7629-clk.h>
+#include <dt-bindings/power/mt7622-power.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/reset/mt7629-resets.h>
+
+/ {
+ compatible = "mediatek,mt7629";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "mediatek,mt6589-smp";
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clock-frequency = <1250000000>;
+ cci-control-port = <&cci_control2>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ clock-frequency = <1250000000>;
+ cci-control-port = <&cci_control2>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ };
+
+ clk20m: oscillator@0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20000000>;
+ clock-output-names = "clk20m";
+ };
+
+ clk40m: oscillator@1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <40000000>;
+ clock-output-names = "clkxtal";
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <20000000>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ infracfg: syscon@10000000 {
+ compatible = "mediatek,mt7629-infracfg", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pericfg: syscon@10002000 {
+ compatible = "mediatek,mt7629-pericfg", "syscon";
+ reg = <0 0x10002000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ scpsys: scpsys@10006000 {
+ compatible = "mediatek,mt7629-scpsys",
+ "mediatek,mt7622-scpsys";
+ #power-domain-cells = <1>;
+ reg = <0 0x10006000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_HIF_SEL>;
+ clock-names = "hif_sel";
+ assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
+ infracfg = <&infracfg>;
+ };
+
+ timer: timer@10009000 {
+ compatible = "mediatek,mt7629-timer",
+ "mediatek,mt6765-timer";
+ reg = <0 0x10009000 0 0x60>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk20m>;
+ clock-names = "clk20m";
+ };
+
+ sysirq: interrupt-controller@10200a80 {
+ compatible = "mediatek,mt7629-sysirq",
+ "mediatek,mt6577-sysirq";
+ reg = <0 0x10200a80 0 0x20>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ };
+
+ apmixedsys: syscon@10209000 {
+ compatible = "mediatek,mt7629-apmixedsys", "syscon";
+ reg = <0 0x10209000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ rng: rng@1020f000 {
+ compatible = "mediatek,mt7629-rng",
+ "mediatek,mt7623-rng";
+ reg = <0 0x1020f000 0 0x100>;
+ clocks = <&infracfg CLK_INFRA_TRNG_PD>;
+ clock-names = "rng";
+ };
+
+ topckgen: syscon@10210000 {
+ compatible = "mediatek,mt7629-topckgen", "syscon";
+ reg = <0 0x10210000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ watchdog: watchdog@10212000 {
+ compatible = "mediatek,mt7629-wdt",
+ "mediatek,mt6589-wdt";
+ reg = <0 0x10212000 0 0x100>;
+ };
+
+ pio: pinctrl@10217000 {
+ compatible = "mediatek,mt7629-pinctrl";
+ reg = <0 0x10217000 0 0x8000>,
+ <0 0x10005000 0 0x1000>;
+ reg-names = "base", "eint";
+ gpio-controller;
+ gpio-ranges = <&pio 0 0 79>;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ };
+
+ gic: interrupt-controller@10300000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10310000 0 0x1000>,
+ <0 0x10320000 0 0x1000>,
+ <0 0x10340000 0 0x2000>,
+ <0 0x10360000 0 0x2000>;
+ };
+
+ cci: cci@10390000 {
+ compatible = "arm,cci-400";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0x10390000 0 0x1000>;
+ ranges = <0 0 0x10390000 0x10000>;
+
+ cci_control0: slave-if@1000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace-lite";
+ reg = <0x1000 0x1000>;
+ };
+
+ cci_control1: slave-if@4000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x4000 0x1000>;
+ };
+
+ cci_control2: slave-if@5000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x5000 0x1000>;
+ };
+
+ pmu@9000 {
+ compatible = "arm,cci-400-pmu,r1";
+ reg = <0x9000 0x5000>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt7629-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&pericfg CLK_PERI_UART0_PD>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt7629-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x400>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&pericfg CLK_PERI_UART1_PD>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11004000 {
+ compatible = "mediatek,mt7629-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x400>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&pericfg CLK_PERI_UART2_PD>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ i2c: i2c@11007000 {
+ compatible = "mediatek,mt7629-i2c",
+ "mediatek,mt2712-i2c";
+ reg = <0 0x11007000 0 0x90>,
+ <0 0x11000100 0 0x80>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <4>;
+ clocks = <&pericfg CLK_PERI_I2C0_PD>,
+ <&pericfg CLK_PERI_AP_DMA_PD>;
+ clock-names = "main", "dma";
+ assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi: spi@1100a000 {
+ compatible = "mediatek,mt7629-spi",
+ "mediatek,mt7622-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x1100a000 0 0x100>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+ <&topckgen CLK_TOP_SPI0_SEL>,
+ <&pericfg CLK_PERI_SPI0_PD>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ qspi: spi@11014000 {
+ compatible = "mediatek,mt7629-nor",
+ "mediatek,mt8173-nor";
+ reg = <0 0x11014000 0 0xe0>;
+ clocks = <&pericfg CLK_PERI_FLASH_PD>,
+ <&topckgen CLK_TOP_FLASH_SEL>;
+ clock-names = "spi", "sf";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ ssusbsys: syscon@1a000000 {
+ compatible = "mediatek,mt7629-ssusbsys", "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ ssusb: usb@1a0c0000 {
+ compatible = "mediatek,mt7629-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x1a0c0000 0 0x01000>,
+ <0 0x1a0c3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
+ <&ssusbsys CLK_SSUSB_REF_EN>,
+ <&ssusbsys CLK_SSUSB_MCU_EN>,
+ <&ssusbsys CLK_SSUSB_DMA_EN>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+ assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
+ <&topckgen CLK_TOP_SATA_SEL>,
+ <&topckgen CLK_TOP_HIF_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
+ <&topckgen CLK_TOP_UNIVPLL2_D4>,
+ <&topckgen CLK_TOP_UNIVPLL1_D2>;
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>;
+ status = "disabled";
+ };
+
+ u3phy1: usb-phy@1a0c4000 {
+ compatible = "mediatek,generic-tphy-v1";
+ reg = <0 0x1a0c4000 0 0x300>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ u2port0: usb-phy@1a0c4300 {
+ reg = <0 0x1a0c4300 0 0x100>;
+ clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port0: usb-phy@1a1c4900 {
+ reg = <0 0x1a1c4900 0 0x700>;
+ clocks = <&clk20m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+ pciesys: syscon@1a100800 {
+ compatible = "mediatek,mt7629-pciesys", "syscon";
+ reg = <0 0x1a100800 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pcie: pcie@1a140000 {
+ compatible = "mediatek,mt7629-pcie";
+ device_type = "pci";
+ reg = <0 0x1a140000 0 0x1000>,
+ <0 0x1a145000 0 0x1000>;
+ reg-names = "subsys", "port1";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
+ <&pciesys CLK_PCIE_P0_AHB_EN>,
+ <&pciesys CLK_PCIE_P1_AUX_EN>,
+ <&pciesys CLK_PCIE_P1_AXI_EN>,
+ <&pciesys CLK_PCIE_P1_OBFF_EN>,
+ <&pciesys CLK_PCIE_P1_PIPE_EN>;
+ clock-names = "sys_ck1", "ahb_ck1",
+ "aux_ck1", "axi_ck1",
+ "obff_ck1", "pipe_ck1";
+ assigned-clocks = <&topckgen CLK_TOP_SATA_SEL>,
+ <&topckgen CLK_TOP_AXI_SEL>,
+ <&topckgen CLK_TOP_HIF_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>,
+ <&topckgen CLK_TOP_SYSPLL1_D2>,
+ <&topckgen CLK_TOP_UNIVPLL1_D2>;
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ bus-range = <0x00 0xff>;
+ status = "disabled";
+ ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x10000000>;
+
+ pcie@1,0 {
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ ethsys: syscon@1b000000 {
+ compatible = "mediatek,mt7629-ethsys", "syscon";
+ reg = <0 0x1b000000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ sgmiisys0: syscon@1b128000 {
+ compatible = "mediatek,mt7629-sgmiisys", "syscon";
+ reg = <0 0x1b128000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ sgmiisys1: syscon@1b130000 {
+ compatible = "mediatek,mt7629-sgmiisys", "syscon";
+ reg = <0 0x1b130000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+};
diff --git a/include/dt-bindings/reset/mt7629-resets.h b/include/dt-bindings/reset/mt7629-resets.h
new file mode 100644
index 0000000..6bb8573
--- /dev/null
+++ b/include/dt-bindings/reset/mt7629-resets.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7629
+#define _DT_BINDINGS_RESET_CONTROLLER_MT7629
+
+/* INFRACFG resets */
+#define MT7629_INFRA_EMI_MPU_RST 0
+#define MT7629_INFRA_UART5_RST 2
+#define MT7629_INFRA_CIRQ_EINT_RST 3
+#define MT7629_INFRA_APXGPT_RST 4
+#define MT7629_INFRA_SCPSYS_RST 5
+#define MT7629_INFRA_KP_RST 6
+#define MT7629_INFRA_SPI1_RST 7
+#define MT7629_INFRA_SPI4_RST 8
+#define MT7629_INFRA_SYSTIMER_RST 9
+#define MT7629_INFRA_IRRX_RST 10
+#define MT7629_INFRA_AO_BUS_RST 16
+#define MT7629_INFRA_EMI_RST 32
+#define MT7629_INFRA_APMIXED_RST 35
+#define MT7629_INFRA_MIPI_RST 36
+#define MT7629_INFRA_TRNG_RST 37
+#define MT7629_INFRA_SYSCIRQ_RST 38
+#define MT7629_INFRA_MIPI_CSI_RST 39
+#define MT7629_INFRA_GCE_FAXI_RST 40
+#define MT7629_INFRA_I2C_SRAM_RST 41
+#define MT7629_INFRA_IOMMU_RST 47
+
+/* PERICFG resets */
+#define MT7629_PERI_UART0_SW_RST 0
+#define MT7629_PERI_UART1_SW_RST 1
+#define MT7629_PERI_UART2_SW_RST 2
+#define MT7629_PERI_BTIF_SW_RST 6
+#define MT7629_PERI_PWN_SW_RST 8
+#define MT7629_PERI_DMA_SW_RST 11
+#define MT7629_PERI_NFI_SW_RST 14
+#define MT7629_PERI_I2C0_SW_RST 22
+#define MT7629_PERI_SPI0_SW_RST 33
+#define MT7629_PERI_SPI1_SW_RST 34
+#define MT7629_PERI_FLASHIF_SW_RST 36
+
+/* PCIe Subsystem resets */
+#define MT7629_PCIE1_CORE_RST 19
+#define MT7629_PCIE1_MMIO_RST 20
+#define MT7629_PCIE1_HRST 21
+#define MT7629_PCIE1_USER_RST 22
+#define MT7629_PCIE1_PIPE_RST 23
+#define MT7629_PCIE0_CORE_RST 27
+#define MT7629_PCIE0_MMIO_RST 28
+#define MT7629_PCIE0_HRST 29
+#define MT7629_PCIE0_USER_RST 30
+#define MT7629_PCIE0_PIPE_RST 31
+
+/* SSUSB Subsystem resets */
+#define MT7629_SSUSB_PHY_PWR_RST 3
+#define MT7629_SSUSB_MAC_PWR_RST 4
+
+/* ETH Subsystem resets */
+#define MT7629_ETHSYS_SYS_RST 0
+#define MT7629_ETHSYS_MCM_RST 2
+#define MT7629_ETHSYS_HSDMA_RST 5
+#define MT7629_ETHSYS_FE_RST 6
+#define MT7629_ETHSYS_ESW_RST 16
+#define MT7629_ETHSYS_GMAC_RST 23
+#define MT7629_ETHSYS_EPHY_RST 24
+#define MT7629_ETHSYS_CRYPTO_RST 29
+#define MT7629_ETHSYS_PPE_RST 31
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7629 */
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 1/7] Revert "ARM: mediatek: add MT7623a smp bringup code"
2019-01-29 4:28 [PATCH 1/7] Revert "ARM: mediatek: add MT7623a smp bringup code" Ryder Lee
` (5 preceding siblings ...)
2019-01-29 4:31 ` [PATCH 7/7] arm: dts: mediatek: add basic support for MT7629 SoC Ryder Lee
@ 2019-02-07 16:47 ` Matthias Brugger
6 siblings, 0 replies; 14+ messages in thread
From: Matthias Brugger @ 2019-02-07 16:47 UTC (permalink / raw)
To: Ryder Lee
Cc: Rob Herring, Sean Wang, Weijie Gao, Roy Luo, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
On 29/01/2019 05:28, Ryder Lee wrote:
> This reverts commit 3b99ab7deca1e5f4229b4bdecd005d71e22cfc60.
>
> The compatible "mediatek,mt7623a" is useless, so remove it.
>
> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
pushed to v5.0-next/soc
Thanks!
> ---
> arch/arm/mach-mediatek/mediatek.c | 2 --
> arch/arm/mach-mediatek/platsmp.c | 1 -
> 2 files changed, 3 deletions(-)
>
> diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
> index 6910b4e..c3cf215 100644
> --- a/arch/arm/mach-mediatek/mediatek.c
> +++ b/arch/arm/mach-mediatek/mediatek.c
> @@ -30,7 +30,6 @@ static void __init mediatek_timer_init(void)
>
> if (of_machine_is_compatible("mediatek,mt6589") ||
> of_machine_is_compatible("mediatek,mt7623") ||
> - of_machine_is_compatible("mediatek,mt7623a") ||
> of_machine_is_compatible("mediatek,mt8135") ||
> of_machine_is_compatible("mediatek,mt8127")) {
> /* turn on GPT6 which ungates arch timer clocks */
> @@ -50,7 +49,6 @@ static void __init mediatek_timer_init(void)
> "mediatek,mt6589",
> "mediatek,mt6592",
> "mediatek,mt7623",
> - "mediatek,mt7623a",
> "mediatek,mt8127",
> "mediatek,mt8135",
> NULL,
> diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c
> index 6882ff0..51e8556 100644
> --- a/arch/arm/mach-mediatek/platsmp.c
> +++ b/arch/arm/mach-mediatek/platsmp.c
> @@ -60,7 +60,6 @@ struct mtk_smp_boot_info {
> static const struct of_device_id mtk_smp_boot_infos[] __initconst = {
> { .compatible = "mediatek,mt6589", .data = &mtk_mt6589_boot },
> { .compatible = "mediatek,mt7623", .data = &mtk_mt7623_boot },
> - { .compatible = "mediatek,mt7623a", .data = &mtk_mt7623_boot },
> {},
> };
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 5/7] dt-bindings: interrupt-controller: update bindings for MT7623
2019-01-29 4:31 ` [PATCH 5/7] dt-bindings: interrupt-controller: update bindings for MT7623 Ryder Lee
@ 2019-02-07 17:11 ` Matthias Brugger
2019-02-08 9:25 ` Marc Zyngier
0 siblings, 1 reply; 14+ messages in thread
From: Matthias Brugger @ 2019-02-07 17:11 UTC (permalink / raw)
To: Ryder Lee, Marc Zyngier
Cc: Rob Herring, Sean Wang, Weijie Gao, Roy Luo, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
On 29/01/2019 05:31, Ryder Lee wrote:
> This adds missing bindings for MT7623 sysirq.
>
> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Marc, if you don't have any objections, I'll take this through my tree.
Regards,
Matthias
> ---
> .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> index 8da481c..e8b3688 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> @@ -9,6 +9,7 @@ Required properties:
> "mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
> "mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
> "mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
> + "mediatek,mt7623-sysirq", "mediatek,mt6577-sysirq": for MT7623
> "mediatek,mt7629-sysirq", "mediatek,mt6577-sysirq": for MT7629
> "mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
> "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 5/7] dt-bindings: interrupt-controller: update bindings for MT7623
2019-02-07 17:11 ` Matthias Brugger
@ 2019-02-08 9:25 ` Marc Zyngier
0 siblings, 0 replies; 14+ messages in thread
From: Marc Zyngier @ 2019-02-08 9:25 UTC (permalink / raw)
To: Matthias Brugger, Ryder Lee
Cc: Rob Herring, Sean Wang, Weijie Gao, Roy Luo, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
On 07/02/2019 17:11, Matthias Brugger wrote:
>
>
> On 29/01/2019 05:31, Ryder Lee wrote:
>> This adds missing bindings for MT7623 sysirq.
>>
>> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
>
> Marc, if you don't have any objections, I'll take this through my tree.
Sure, feel free to.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 4/7] dt-bindings: mediatek: update bindings for MT7629 SoC
2019-01-29 4:31 ` [PATCH 4/7] dt-bindings: mediatek: update bindings for MT7629 SoC Ryder Lee
@ 2019-02-08 12:28 ` Matthias Brugger
0 siblings, 0 replies; 14+ messages in thread
From: Matthias Brugger @ 2019-02-08 12:28 UTC (permalink / raw)
To: Ryder Lee
Cc: Rob Herring, Sean Wang, Weijie Gao, Roy Luo, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
On 29/01/2019 05:31, Ryder Lee wrote:
> This updates bindings for MT7629 SoC, which includes very basic items
> such as system timer, UART, sysirq and scpsys unit.
>
> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
> ---
> .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt | 5 +++--
> Documentation/devicetree/bindings/serial/mtk-uart.txt | 3 ++-
> Documentation/devicetree/bindings/soc/mediatek/scpsys.txt | 5 +++--
> Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 7 ++++---
So we touching different sub systems here. Please consider either adding all
maintainers to the new version or split it up in smaller patches.
More comments below.
> 4 files changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> index 33a98eb..8da481c 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> @@ -1,6 +1,6 @@
> -+Mediatek MT65xx/MT67xx/MT81xx sysirq
> +MediaTek sysirq
>
> -Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
> +MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
> interrupt.
>
> Required properties:
> @@ -9,6 +9,7 @@ Required properties:
> "mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
> "mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
> "mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
> + "mediatek,mt7629-sysirq", "mediatek,mt6577-sysirq": for MT7629
> "mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
> "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
> "mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765
> diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
> index 742cb47..4910f63 100644
> --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
> +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
> @@ -1,4 +1,4 @@
> -* Mediatek Universal Asynchronous Receiver/Transmitter (UART)
> +* MediaTek Universal Asynchronous Receiver/Transmitter (UART)
>
> Required properties:
> - compatible should contain:
> @@ -13,6 +13,7 @@ Required properties:
> * "mediatek,mt6797-uart" for MT6797 compatible UARTS
> * "mediatek,mt7622-uart" for MT7622 compatible UARTS
> * "mediatek,mt7623-uart" for MT7623 compatible UARTS
> + * "mediatek,mt7629-uart" for MT7629 compatible UARTS
> * "mediatek,mt8127-uart" for MT8127 compatible UARTS
> * "mediatek,mt8135-uart" for MT8135 compatible UARTS
> * "mediatek,mt8173-uart" for MT8173 compatible UARTS
> diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
> index d6fe16f..876693a 100644
> --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
> +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
> @@ -23,6 +23,7 @@ Required properties:
> - "mediatek,mt7622-scpsys"
> - "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC
> - "mediatek,mt7623a-scpsys": For MT7623A SoC
> + - "mediatek,mt7629-scpsys", "mediatek,mt7622-scpsys": For MT7629 SoC
> - "mediatek,mt8173-scpsys"
> - #power-domain-cells: Must be 1
> - reg: Address range of the SCPSYS unit
> @@ -33,8 +34,8 @@ Required properties:
> Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
> Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
> Required clocks for MT6797: "mm", "mfg", "vdec"
> - Required clocks for MT7622: "hif_sel"
> - Required clocks for MT7622A: "ethif"
> + Required clocks for MT7622 or MT7629: "hif_sel"
> + Required clocks for MT7623A: "ethif"
Please make a seperate patch for sypsys mentioning that you fix the description
here.
> Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
>
> Optional properties:
> diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
> index 18d4d01..12b6d06 100644
> --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
> +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
> @@ -1,7 +1,7 @@
> -Mediatek Timers
> +MediaTek Timers
> ---------------
>
> -Mediatek SoCs have two different timers on different platforms,
> +MediaTek SoCs have two different timers on different platforms,
> - GPT (General Purpose Timer)
> - SYST (System Timer)
>
> @@ -17,7 +17,8 @@ Required properties:
> * "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
> * "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
> * "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)
> - * "mediatek,mt6765-timer" for MT6765 compatible timers (SYST)
> + * "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)
> + * "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST)
Can you order the bindings?
Regards,
Matthias
> - reg: Should contain location and length for timer register.
> - clocks: Should contain system clock.
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 7/7] arm: dts: mediatek: add basic support for MT7629 SoC
2019-01-29 4:31 ` [PATCH 7/7] arm: dts: mediatek: add basic support for MT7629 SoC Ryder Lee
@ 2019-02-08 12:30 ` Matthias Brugger
2019-02-25 14:37 ` Rob Herring
1 sibling, 0 replies; 14+ messages in thread
From: Matthias Brugger @ 2019-02-08 12:30 UTC (permalink / raw)
To: Ryder Lee
Cc: Rob Herring, Sean Wang, Weijie Gao, Roy Luo, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
On 29/01/2019 05:31, Ryder Lee wrote:
> This adds basic support for MT7629 reference board.
>
> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
> ---
> The I2C node depends on https://patchwork.kernel.org/patch/10772837/
> The PCIe node depends on https://patchwork.kernel.org/patch/10773637/
Not all of them are merged now. So postponing this for now.
Apart from 4/7 and 7/7 I'll take the rest through my tree.
Thanks a lot,
Matthias
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/mt7629-rfb.dts | 234 +++++++++++++++++
> arch/arm/boot/dts/mt7629.dtsi | 416 ++++++++++++++++++++++++++++++
> include/dt-bindings/reset/mt7629-resets.h | 71 +++++
> 4 files changed, 722 insertions(+)
> create mode 100644 arch/arm/boot/dts/mt7629-rfb.dts
> create mode 100644 arch/arm/boot/dts/mt7629.dtsi
> create mode 100644 include/dt-bindings/reset/mt7629-resets.h
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index bd40148..a5a6d9f 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1231,6 +1231,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
> mt7623a-rfb-nand.dtb \
> mt7623n-rfb-emmc.dtb \
> mt7623n-bananapi-bpi-r2.dtb \
> + mt7629-rfb.dtb \
> mt8127-moose.dtb \
> mt8135-evbp1.dtb
> dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
> diff --git a/arch/arm/boot/dts/mt7629-rfb.dts b/arch/arm/boot/dts/mt7629-rfb.dts
> new file mode 100644
> index 0000000..0878a14
> --- /dev/null
> +++ b/arch/arm/boot/dts/mt7629-rfb.dts
> @@ -0,0 +1,234 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + * Author: Ryder Lee <ryder.lee@mediatek.com>
> + */
> +
> +/dts-v1/;
> +#include <dt-bindings/input/input.h>
> +#include "mt7629.dtsi"
> +
> +/ {
> + model = "MediaTek MT7629 reference board";
> + compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + bootargs = "earlycon=uart8250,mmio32,0x11002000";
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + reset {
> + label = "factory";
> + linux,code = <KEY_RESTART>;
> + gpios = <&pio 60 GPIO_ACTIVE_LOW>;
> + };
> +
> + wps {
> + label = "wps";
> + linux,code = <KEY_WPS_BUTTON>;
> + gpios = <&pio 58 GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0 0x40000000 0 0x10000000>;
> + };
> +
> + reg_3p3v: regulator-3p3v {
> + compatible = "regulator-fixed";
> + regulator-name = "fixed-3.3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + reg_5v: regulator-5v {
> + compatible = "regulator-fixed";
> + regulator-name = "fixed-5V";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +};
> +
> +&i2c {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c_pins>;
> + status = "okay";
> +};
> +
> +&qspi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&qspi_pins>;
> + status = "okay";
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition@00000 {
> + label = "Bootloader";
> + reg = <0x00000 0x0060000>;
> + };
> +
> + partition@60000 {
> + label = "Config";
> + reg = <0x60000 0x0010000>;
> + };
> +
> + partition@70000 {
> + label = "Factory";
> + reg = <0x70000 0x0040000>;
> + };
> +
> + partition@b0000 {
> + label = "Kernel";
> + reg = <0xb0000 0xb50000>;
> + };
> + };
> +};
> +
> +&pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie_pins>;
> + status = "okay";
> +
> + pcie@1,0 {
> + status = "okay";
> + };
> +};
> +
> +&pio {
> + eth_pins: eth-pins {
> + mux {
> + function = "eth";
> + groups = "mdc_mdio";
> + };
> + };
> +
> + ephy_leds_pins: ephy-leds-pins {
> + mux {
> + function = "led";
> + groups = "gphy_leds_0", "ephy_leds";
> + };
> + };
> +
> + i2c_pins: i2c-pins {
> + mux {
> + function = "i2c";
> + groups = "i2c_0";
> + };
> +
> + conf {
> + pins = "I2C_SDA", "I2C_SCL";
> + drive-strength = <4>;
> + bias-disable;
> + };
> + };
> +
> + pcie_pins: pcie-pins {
> + mux {
> + function = "pcie";
> + groups = "pcie_clkreq",
> + "pcie_pereset",
> + "pcie_wake";
> + };
> + };
> +
> + pwm_pins: pwm-pins {
> + mux {
> + function = "pwm";
> + groups = "pwm_0";
> + };
> + };
> +
> + /* Serial NAND is shared pin with SPI-NOR */
> + serial_nand_pins: serial-nand-pins {
> + mux {
> + function = "flash";
> + groups = "snfi";
> + };
> + };
> +
> + spi_pins: spi-pins {
> + mux {
> + function = "spi";
> + groups = "spi_0";
> + };
> + };
> +
> + /* SPI-NOR is shared pin with serial NAND */
> + qspi_pins: qspi-pins {
> + mux {
> + function = "flash";
> + groups = "spi_nor";
> + };
> + };
> +
> + uart0_pins: uart0-pins {
> + mux {
> + function = "uart";
> + groups = "uart0_txd_rxd" ;
> + };
> + };
> +
> + uart1_pins: uart1-pins {
> + mux {
> + function = "uart";
> + groups = "uart1_0_tx_rx" ;
> + };
> + };
> +
> + uart2_pins: uart2-pins {
> + mux {
> + function = "uart";
> + groups = "uart2_0_txd_rxd" ;
> + };
> + };
> +
> + watchdog_pins: watchdog-pins {
> + mux {
> + function = "watchdog";
> + groups = "watchdog";
> + };
> + };
> +};
> +
> +&spi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi_pins>;
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins>;
> + status = "okay";
> +};
> +
> +&ssusb {
> + vusb33-supply = <®_3p3v>;
> + vbus-supply = <®_5v>;
> + status = "okay";
> +};
> +
> +&u3phy1 {
> + status = "okay";
> +};
> +
> +&watchdog {
> + pinctrl-names = "default";
> + pinctrl-0 = <&watchdog_pins>;
> + status = "okay";
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi
> new file mode 100644
> index 0000000..2b4410a
> --- /dev/null
> +++ b/arch/arm/boot/dts/mt7629.dtsi
> @@ -0,0 +1,416 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + *
> + * Author: Ryder Lee <ryder.lee@mediatek.com>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/mt7629-clk.h>
> +#include <dt-bindings/power/mt7622-power.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/reset/mt7629-resets.h>
> +
> +/ {
> + compatible = "mediatek,mt7629";
> + interrupt-parent = <&sysirq>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + enable-method = "mediatek,mt6589-smp";
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x0>;
> + clock-frequency = <1250000000>;
> + cci-control-port = <&cci_control2>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x1>;
> + clock-frequency = <1250000000>;
> + cci-control-port = <&cci_control2>;
> + };
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a7-pmu";
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-affinity = <&cpu0>, <&cpu1>;
> + };
> +
> + clk20m: oscillator@0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <20000000>;
> + clock-output-names = "clk20m";
> + };
> +
> + clk40m: oscillator@1 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <40000000>;
> + clock-output-names = "clkxtal";
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + clock-frequency = <20000000>;
> + arm,cpu-registers-not-fw-configured;
> + };
> +
> + infracfg: syscon@10000000 {
> + compatible = "mediatek,mt7629-infracfg", "syscon";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + pericfg: syscon@10002000 {
> + compatible = "mediatek,mt7629-pericfg", "syscon";
> + reg = <0 0x10002000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + scpsys: scpsys@10006000 {
> + compatible = "mediatek,mt7629-scpsys",
> + "mediatek,mt7622-scpsys";
> + #power-domain-cells = <1>;
> + reg = <0 0x10006000 0 0x1000>;
> + clocks = <&topckgen CLK_TOP_HIF_SEL>;
> + clock-names = "hif_sel";
> + assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
> + infracfg = <&infracfg>;
> + };
> +
> + timer: timer@10009000 {
> + compatible = "mediatek,mt7629-timer",
> + "mediatek,mt6765-timer";
> + reg = <0 0x10009000 0 0x60>;
> + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk20m>;
> + clock-names = "clk20m";
> + };
> +
> + sysirq: interrupt-controller@10200a80 {
> + compatible = "mediatek,mt7629-sysirq",
> + "mediatek,mt6577-sysirq";
> + reg = <0 0x10200a80 0 0x20>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + };
> +
> + apmixedsys: syscon@10209000 {
> + compatible = "mediatek,mt7629-apmixedsys", "syscon";
> + reg = <0 0x10209000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + rng: rng@1020f000 {
> + compatible = "mediatek,mt7629-rng",
> + "mediatek,mt7623-rng";
> + reg = <0 0x1020f000 0 0x100>;
> + clocks = <&infracfg CLK_INFRA_TRNG_PD>;
> + clock-names = "rng";
> + };
> +
> + topckgen: syscon@10210000 {
> + compatible = "mediatek,mt7629-topckgen", "syscon";
> + reg = <0 0x10210000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + watchdog: watchdog@10212000 {
> + compatible = "mediatek,mt7629-wdt",
> + "mediatek,mt6589-wdt";
> + reg = <0 0x10212000 0 0x100>;
> + };
> +
> + pio: pinctrl@10217000 {
> + compatible = "mediatek,mt7629-pinctrl";
> + reg = <0 0x10217000 0 0x8000>,
> + <0 0x10005000 0 0x1000>;
> + reg-names = "base", "eint";
> + gpio-controller;
> + gpio-ranges = <&pio 0 0 79>;
> + #gpio-cells = <2>;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&gic>;
> + };
> +
> + gic: interrupt-controller@10300000 {
> + compatible = "arm,gic-400";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + reg = <0 0x10310000 0 0x1000>,
> + <0 0x10320000 0 0x1000>,
> + <0 0x10340000 0 0x2000>,
> + <0 0x10360000 0 0x2000>;
> + };
> +
> + cci: cci@10390000 {
> + compatible = "arm,cci-400";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0 0x10390000 0 0x1000>;
> + ranges = <0 0 0x10390000 0x10000>;
> +
> + cci_control0: slave-if@1000 {
> + compatible = "arm,cci-400-ctrl-if";
> + interface-type = "ace-lite";
> + reg = <0x1000 0x1000>;
> + };
> +
> + cci_control1: slave-if@4000 {
> + compatible = "arm,cci-400-ctrl-if";
> + interface-type = "ace";
> + reg = <0x4000 0x1000>;
> + };
> +
> + cci_control2: slave-if@5000 {
> + compatible = "arm,cci-400-ctrl-if";
> + interface-type = "ace";
> + reg = <0x5000 0x1000>;
> + };
> +
> + pmu@9000 {
> + compatible = "arm,cci-400-pmu,r1";
> + reg = <0x9000 0x5000>;
> + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + uart0: serial@11002000 {
> + compatible = "mediatek,mt7629-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11002000 0 0x400>;
> + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_UART_SEL>,
> + <&pericfg CLK_PERI_UART0_PD>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + uart1: serial@11003000 {
> + compatible = "mediatek,mt7629-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11003000 0 0x400>;
> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_UART_SEL>,
> + <&pericfg CLK_PERI_UART1_PD>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + uart2: serial@11004000 {
> + compatible = "mediatek,mt7629-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11004000 0 0x400>;
> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_UART_SEL>,
> + <&pericfg CLK_PERI_UART2_PD>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + i2c: i2c@11007000 {
> + compatible = "mediatek,mt7629-i2c",
> + "mediatek,mt2712-i2c";
> + reg = <0 0x11007000 0 0x90>,
> + <0 0x11000100 0 0x80>;
> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <4>;
> + clocks = <&pericfg CLK_PERI_I2C0_PD>,
> + <&pericfg CLK_PERI_AP_DMA_PD>;
> + clock-names = "main", "dma";
> + assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + spi: spi@1100a000 {
> + compatible = "mediatek,mt7629-spi",
> + "mediatek,mt7622-spi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0 0x1100a000 0 0x100>;
> + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
> + <&topckgen CLK_TOP_SPI0_SEL>,
> + <&pericfg CLK_PERI_SPI0_PD>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + status = "disabled";
> + };
> +
> + qspi: spi@11014000 {
> + compatible = "mediatek,mt7629-nor",
> + "mediatek,mt8173-nor";
> + reg = <0 0x11014000 0 0xe0>;
> + clocks = <&pericfg CLK_PERI_FLASH_PD>,
> + <&topckgen CLK_TOP_FLASH_SEL>;
> + clock-names = "spi", "sf";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + ssusbsys: syscon@1a000000 {
> + compatible = "mediatek,mt7629-ssusbsys", "syscon";
> + reg = <0 0x1a000000 0 0x1000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + ssusb: usb@1a0c0000 {
> + compatible = "mediatek,mt7629-xhci",
> + "mediatek,mtk-xhci";
> + reg = <0 0x1a0c0000 0 0x01000>,
> + <0 0x1a0c3e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
> + <&ssusbsys CLK_SSUSB_REF_EN>,
> + <&ssusbsys CLK_SSUSB_MCU_EN>,
> + <&ssusbsys CLK_SSUSB_DMA_EN>;
> + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
> + assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
> + <&topckgen CLK_TOP_SATA_SEL>,
> + <&topckgen CLK_TOP_HIF_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
> + <&topckgen CLK_TOP_UNIVPLL2_D4>,
> + <&topckgen CLK_TOP_UNIVPLL1_D2>;
> + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
> + phys = <&u2port0 PHY_TYPE_USB2>,
> + <&u3port0 PHY_TYPE_USB3>;
> + status = "disabled";
> + };
> +
> + u3phy1: usb-phy@1a0c4000 {
> + compatible = "mediatek,generic-tphy-v1";
> + reg = <0 0x1a0c4000 0 0x300>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + u2port0: usb-phy@1a0c4300 {
> + reg = <0 0x1a0c4300 0 0x100>;
> + clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> +
> + u3port0: usb-phy@1a1c4900 {
> + reg = <0 0x1a1c4900 0 0x700>;
> + clocks = <&clk20m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> + };
> +
> + pciesys: syscon@1a100800 {
> + compatible = "mediatek,mt7629-pciesys", "syscon";
> + reg = <0 0x1a100800 0 0x1000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + pcie: pcie@1a140000 {
> + compatible = "mediatek,mt7629-pcie";
> + device_type = "pci";
> + reg = <0 0x1a140000 0 0x1000>,
> + <0 0x1a145000 0 0x1000>;
> + reg-names = "subsys", "port1";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
> + <&pciesys CLK_PCIE_P0_AHB_EN>,
> + <&pciesys CLK_PCIE_P1_AUX_EN>,
> + <&pciesys CLK_PCIE_P1_AXI_EN>,
> + <&pciesys CLK_PCIE_P1_OBFF_EN>,
> + <&pciesys CLK_PCIE_P1_PIPE_EN>;
> + clock-names = "sys_ck1", "ahb_ck1",
> + "aux_ck1", "axi_ck1",
> + "obff_ck1", "pipe_ck1";
> + assigned-clocks = <&topckgen CLK_TOP_SATA_SEL>,
> + <&topckgen CLK_TOP_AXI_SEL>,
> + <&topckgen CLK_TOP_HIF_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>,
> + <&topckgen CLK_TOP_SYSPLL1_D2>,
> + <&topckgen CLK_TOP_UNIVPLL1_D2>;
> + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
> + bus-range = <0x00 0xff>;
> + status = "disabled";
> + ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x10000000>;
> +
> + pcie@1,0 {
> + reg = <0x0800 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + ranges;
> + status = "disabled";
> +
> + num-lanes = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie_intc1 0>,
> + <0 0 0 2 &pcie_intc1 1>,
> + <0 0 0 3 &pcie_intc1 2>,
> + <0 0 0 4 &pcie_intc1 3>;
> + pcie_intc1: interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> + };
> + };
> +
> + ethsys: syscon@1b000000 {
> + compatible = "mediatek,mt7629-ethsys", "syscon";
> + reg = <0 0x1b000000 0 0x1000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + sgmiisys0: syscon@1b128000 {
> + compatible = "mediatek,mt7629-sgmiisys", "syscon";
> + reg = <0 0x1b128000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + sgmiisys1: syscon@1b130000 {
> + compatible = "mediatek,mt7629-sgmiisys", "syscon";
> + reg = <0 0x1b130000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +};
> diff --git a/include/dt-bindings/reset/mt7629-resets.h b/include/dt-bindings/reset/mt7629-resets.h
> new file mode 100644
> index 0000000..6bb8573
> --- /dev/null
> +++ b/include/dt-bindings/reset/mt7629-resets.h
> @@ -0,0 +1,71 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2019 MediaTek Inc.
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7629
> +#define _DT_BINDINGS_RESET_CONTROLLER_MT7629
> +
> +/* INFRACFG resets */
> +#define MT7629_INFRA_EMI_MPU_RST 0
> +#define MT7629_INFRA_UART5_RST 2
> +#define MT7629_INFRA_CIRQ_EINT_RST 3
> +#define MT7629_INFRA_APXGPT_RST 4
> +#define MT7629_INFRA_SCPSYS_RST 5
> +#define MT7629_INFRA_KP_RST 6
> +#define MT7629_INFRA_SPI1_RST 7
> +#define MT7629_INFRA_SPI4_RST 8
> +#define MT7629_INFRA_SYSTIMER_RST 9
> +#define MT7629_INFRA_IRRX_RST 10
> +#define MT7629_INFRA_AO_BUS_RST 16
> +#define MT7629_INFRA_EMI_RST 32
> +#define MT7629_INFRA_APMIXED_RST 35
> +#define MT7629_INFRA_MIPI_RST 36
> +#define MT7629_INFRA_TRNG_RST 37
> +#define MT7629_INFRA_SYSCIRQ_RST 38
> +#define MT7629_INFRA_MIPI_CSI_RST 39
> +#define MT7629_INFRA_GCE_FAXI_RST 40
> +#define MT7629_INFRA_I2C_SRAM_RST 41
> +#define MT7629_INFRA_IOMMU_RST 47
> +
> +/* PERICFG resets */
> +#define MT7629_PERI_UART0_SW_RST 0
> +#define MT7629_PERI_UART1_SW_RST 1
> +#define MT7629_PERI_UART2_SW_RST 2
> +#define MT7629_PERI_BTIF_SW_RST 6
> +#define MT7629_PERI_PWN_SW_RST 8
> +#define MT7629_PERI_DMA_SW_RST 11
> +#define MT7629_PERI_NFI_SW_RST 14
> +#define MT7629_PERI_I2C0_SW_RST 22
> +#define MT7629_PERI_SPI0_SW_RST 33
> +#define MT7629_PERI_SPI1_SW_RST 34
> +#define MT7629_PERI_FLASHIF_SW_RST 36
> +
> +/* PCIe Subsystem resets */
> +#define MT7629_PCIE1_CORE_RST 19
> +#define MT7629_PCIE1_MMIO_RST 20
> +#define MT7629_PCIE1_HRST 21
> +#define MT7629_PCIE1_USER_RST 22
> +#define MT7629_PCIE1_PIPE_RST 23
> +#define MT7629_PCIE0_CORE_RST 27
> +#define MT7629_PCIE0_MMIO_RST 28
> +#define MT7629_PCIE0_HRST 29
> +#define MT7629_PCIE0_USER_RST 30
> +#define MT7629_PCIE0_PIPE_RST 31
> +
> +/* SSUSB Subsystem resets */
> +#define MT7629_SSUSB_PHY_PWR_RST 3
> +#define MT7629_SSUSB_MAC_PWR_RST 4
> +
> +/* ETH Subsystem resets */
> +#define MT7629_ETHSYS_SYS_RST 0
> +#define MT7629_ETHSYS_MCM_RST 2
> +#define MT7629_ETHSYS_HSDMA_RST 5
> +#define MT7629_ETHSYS_FE_RST 6
> +#define MT7629_ETHSYS_ESW_RST 16
> +#define MT7629_ETHSYS_GMAC_RST 23
> +#define MT7629_ETHSYS_EPHY_RST 24
> +#define MT7629_ETHSYS_CRYPTO_RST 29
> +#define MT7629_ETHSYS_PPE_RST 31
> +
> +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7629 */
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/7] dt-bindings: arm: mediatek: add support for MT7622 BPI-R64 and MT7629 RFB
2019-01-29 4:31 ` [PATCH 3/7] dt-bindings: arm: mediatek: add support for MT7622 BPI-R64 and MT7629 RFB Ryder Lee
@ 2019-02-13 20:12 ` Rob Herring
0 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2019-02-13 20:12 UTC (permalink / raw)
To: Matthias Brugger
Cc: Ryder Lee, Sean Wang, Weijie Gao, Roy Luo, devicetree,
linux-kernel,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
moderated list:ARM/Mediatek SoC support
On Mon, Jan 28, 2019 at 10:31 PM Ryder Lee <ryder.lee@mediatek.com> wrote:
>
> Update binding document for MT7622 BPI-R64 and MT7629 reference board.
>
> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
> ---
> Documentation/devicetree/bindings/arm/mediatek.txt | 7 +++++++
> 1 file changed, 7 insertions(+)
Do you plan to apply my patch converting Mediatek to DT schema[1]? I'm
not planning to rebase it now that this one is applied and resend it.
Rob
[1] https://patchwork.ozlabs.org/patch/1007257/
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 7/7] arm: dts: mediatek: add basic support for MT7629 SoC
2019-01-29 4:31 ` [PATCH 7/7] arm: dts: mediatek: add basic support for MT7629 SoC Ryder Lee
2019-02-08 12:30 ` Matthias Brugger
@ 2019-02-25 14:37 ` Rob Herring
1 sibling, 0 replies; 14+ messages in thread
From: Rob Herring @ 2019-02-25 14:37 UTC (permalink / raw)
To: Ryder Lee
Cc: Matthias Brugger, Sean Wang, Weijie Gao, Roy Luo, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
On Tue, Jan 29, 2019 at 12:31:19PM +0800, Ryder Lee wrote:
> This adds basic support for MT7629 reference board.
>
> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
> ---
> The I2C node depends on https://patchwork.kernel.org/patch/10772837/
> The PCIe node depends on https://patchwork.kernel.org/patch/10773637/
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/mt7629-rfb.dts | 234 +++++++++++++++++
> arch/arm/boot/dts/mt7629.dtsi | 416 ++++++++++++++++++++++++++++++
> include/dt-bindings/reset/mt7629-resets.h | 71 +++++
> 4 files changed, 722 insertions(+)
> create mode 100644 arch/arm/boot/dts/mt7629-rfb.dts
> create mode 100644 arch/arm/boot/dts/mt7629.dtsi
> create mode 100644 include/dt-bindings/reset/mt7629-resets.h
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index bd40148..a5a6d9f 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1231,6 +1231,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
> mt7623a-rfb-nand.dtb \
> mt7623n-rfb-emmc.dtb \
> mt7623n-bananapi-bpi-r2.dtb \
> + mt7629-rfb.dtb \
> mt8127-moose.dtb \
> mt8135-evbp1.dtb
> dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
> diff --git a/arch/arm/boot/dts/mt7629-rfb.dts b/arch/arm/boot/dts/mt7629-rfb.dts
> new file mode 100644
> index 0000000..0878a14
> --- /dev/null
> +++ b/arch/arm/boot/dts/mt7629-rfb.dts
> @@ -0,0 +1,234 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + * Author: Ryder Lee <ryder.lee@mediatek.com>
> + */
> +
> +/dts-v1/;
> +#include <dt-bindings/input/input.h>
> +#include "mt7629.dtsi"
> +
> +/ {
> + model = "MediaTek MT7629 reference board";
> + compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + bootargs = "earlycon=uart8250,mmio32,0x11002000";
Just 'earlycon' with no options is all you need if stdout-path is set.
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + reset {
> + label = "factory";
> + linux,code = <KEY_RESTART>;
> + gpios = <&pio 60 GPIO_ACTIVE_LOW>;
> + };
> +
> + wps {
> + label = "wps";
> + linux,code = <KEY_WPS_BUTTON>;
> + gpios = <&pio 58 GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0 0x40000000 0 0x10000000>;
> + };
> +
> + reg_3p3v: regulator-3p3v {
> + compatible = "regulator-fixed";
> + regulator-name = "fixed-3.3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + reg_5v: regulator-5v {
> + compatible = "regulator-fixed";
> + regulator-name = "fixed-5V";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +};
> +
> +&i2c {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c_pins>;
> + status = "okay";
> +};
> +
> +&qspi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&qspi_pins>;
> + status = "okay";
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition@00000 {
All these under a 'partitions' node is the preferred way.
> + label = "Bootloader";
> + reg = <0x00000 0x0060000>;
> + };
> +
> + partition@60000 {
> + label = "Config";
> + reg = <0x60000 0x0010000>;
> + };
> +
> + partition@70000 {
> + label = "Factory";
> + reg = <0x70000 0x0040000>;
> + };
> +
> + partition@b0000 {
> + label = "Kernel";
> + reg = <0xb0000 0xb50000>;
> + };
> + };
> +};
> +
> +&pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie_pins>;
> + status = "okay";
> +
> + pcie@1,0 {
> + status = "okay";
> + };
> +};
> +
> +&pio {
> + eth_pins: eth-pins {
> + mux {
> + function = "eth";
> + groups = "mdc_mdio";
> + };
> + };
> +
> + ephy_leds_pins: ephy-leds-pins {
> + mux {
> + function = "led";
> + groups = "gphy_leds_0", "ephy_leds";
> + };
> + };
> +
> + i2c_pins: i2c-pins {
> + mux {
> + function = "i2c";
> + groups = "i2c_0";
> + };
> +
> + conf {
> + pins = "I2C_SDA", "I2C_SCL";
> + drive-strength = <4>;
> + bias-disable;
> + };
> + };
> +
> + pcie_pins: pcie-pins {
> + mux {
> + function = "pcie";
> + groups = "pcie_clkreq",
> + "pcie_pereset",
> + "pcie_wake";
> + };
> + };
> +
> + pwm_pins: pwm-pins {
> + mux {
> + function = "pwm";
> + groups = "pwm_0";
> + };
> + };
> +
> + /* Serial NAND is shared pin with SPI-NOR */
> + serial_nand_pins: serial-nand-pins {
> + mux {
> + function = "flash";
> + groups = "snfi";
> + };
> + };
> +
> + spi_pins: spi-pins {
> + mux {
> + function = "spi";
> + groups = "spi_0";
> + };
> + };
> +
> + /* SPI-NOR is shared pin with serial NAND */
> + qspi_pins: qspi-pins {
> + mux {
> + function = "flash";
> + groups = "spi_nor";
> + };
> + };
> +
> + uart0_pins: uart0-pins {
> + mux {
> + function = "uart";
> + groups = "uart0_txd_rxd" ;
> + };
> + };
> +
> + uart1_pins: uart1-pins {
> + mux {
> + function = "uart";
> + groups = "uart1_0_tx_rx" ;
> + };
> + };
> +
> + uart2_pins: uart2-pins {
> + mux {
> + function = "uart";
> + groups = "uart2_0_txd_rxd" ;
> + };
> + };
> +
> + watchdog_pins: watchdog-pins {
> + mux {
> + function = "watchdog";
> + groups = "watchdog";
> + };
> + };
> +};
> +
> +&spi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi_pins>;
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins>;
> + status = "okay";
> +};
> +
> +&ssusb {
> + vusb33-supply = <®_3p3v>;
> + vbus-supply = <®_5v>;
> + status = "okay";
> +};
> +
> +&u3phy1 {
> + status = "okay";
> +};
> +
> +&watchdog {
> + pinctrl-names = "default";
> + pinctrl-0 = <&watchdog_pins>;
> + status = "okay";
> +};
> \ No newline at end of file
> diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi
> new file mode 100644
> index 0000000..2b4410a
> --- /dev/null
> +++ b/arch/arm/boot/dts/mt7629.dtsi
> @@ -0,0 +1,416 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + *
> + * Author: Ryder Lee <ryder.lee@mediatek.com>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/mt7629-clk.h>
> +#include <dt-bindings/power/mt7622-power.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/reset/mt7629-resets.h>
> +
> +/ {
> + compatible = "mediatek,mt7629";
> + interrupt-parent = <&sysirq>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + enable-method = "mediatek,mt6589-smp";
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x0>;
> + clock-frequency = <1250000000>;
> + cci-control-port = <&cci_control2>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x1>;
> + clock-frequency = <1250000000>;
> + cci-control-port = <&cci_control2>;
> + };
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a7-pmu";
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-affinity = <&cpu0>, <&cpu1>;
> + };
> +
> + clk20m: oscillator@0 {
Unit-address without reg is not valid, so drop it. Build your dtb with
W=1 (and W=12 preferrably) and fix the warnings like this.
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <20000000>;
> + clock-output-names = "clk20m";
> + };
> +
> + clk40m: oscillator@1 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <40000000>;
> + clock-output-names = "clkxtal";
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + clock-frequency = <20000000>;
> + arm,cpu-registers-not-fw-configured;
> + };
> +
> + infracfg: syscon@10000000 {
Put all the mmio peripherals under a simple-bus node.
> + compatible = "mediatek,mt7629-infracfg", "syscon";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + pericfg: syscon@10002000 {
> + compatible = "mediatek,mt7629-pericfg", "syscon";
> + reg = <0 0x10002000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + scpsys: scpsys@10006000 {
> + compatible = "mediatek,mt7629-scpsys",
> + "mediatek,mt7622-scpsys";
> + #power-domain-cells = <1>;
> + reg = <0 0x10006000 0 0x1000>;
> + clocks = <&topckgen CLK_TOP_HIF_SEL>;
> + clock-names = "hif_sel";
> + assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
> + infracfg = <&infracfg>;
> + };
> +
> + timer: timer@10009000 {
> + compatible = "mediatek,mt7629-timer",
> + "mediatek,mt6765-timer";
> + reg = <0 0x10009000 0 0x60>;
> + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk20m>;
> + clock-names = "clk20m";
> + };
> +
> + sysirq: interrupt-controller@10200a80 {
> + compatible = "mediatek,mt7629-sysirq",
> + "mediatek,mt6577-sysirq";
> + reg = <0 0x10200a80 0 0x20>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + };
> +
> + apmixedsys: syscon@10209000 {
> + compatible = "mediatek,mt7629-apmixedsys", "syscon";
> + reg = <0 0x10209000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + rng: rng@1020f000 {
> + compatible = "mediatek,mt7629-rng",
> + "mediatek,mt7623-rng";
> + reg = <0 0x1020f000 0 0x100>;
> + clocks = <&infracfg CLK_INFRA_TRNG_PD>;
> + clock-names = "rng";
> + };
> +
> + topckgen: syscon@10210000 {
> + compatible = "mediatek,mt7629-topckgen", "syscon";
> + reg = <0 0x10210000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + watchdog: watchdog@10212000 {
> + compatible = "mediatek,mt7629-wdt",
> + "mediatek,mt6589-wdt";
> + reg = <0 0x10212000 0 0x100>;
> + };
> +
> + pio: pinctrl@10217000 {
> + compatible = "mediatek,mt7629-pinctrl";
> + reg = <0 0x10217000 0 0x8000>,
> + <0 0x10005000 0 0x1000>;
> + reg-names = "base", "eint";
> + gpio-controller;
> + gpio-ranges = <&pio 0 0 79>;
> + #gpio-cells = <2>;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&gic>;
> + };
> +
> + gic: interrupt-controller@10300000 {
> + compatible = "arm,gic-400";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + reg = <0 0x10310000 0 0x1000>,
> + <0 0x10320000 0 0x1000>,
> + <0 0x10340000 0 0x2000>,
> + <0 0x10360000 0 0x2000>;
> + };
> +
> + cci: cci@10390000 {
> + compatible = "arm,cci-400";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0 0x10390000 0 0x1000>;
> + ranges = <0 0 0x10390000 0x10000>;
> +
> + cci_control0: slave-if@1000 {
> + compatible = "arm,cci-400-ctrl-if";
> + interface-type = "ace-lite";
> + reg = <0x1000 0x1000>;
> + };
> +
> + cci_control1: slave-if@4000 {
> + compatible = "arm,cci-400-ctrl-if";
> + interface-type = "ace";
> + reg = <0x4000 0x1000>;
> + };
> +
> + cci_control2: slave-if@5000 {
> + compatible = "arm,cci-400-ctrl-if";
> + interface-type = "ace";
> + reg = <0x5000 0x1000>;
> + };
> +
> + pmu@9000 {
> + compatible = "arm,cci-400-pmu,r1";
> + reg = <0x9000 0x5000>;
> + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + uart0: serial@11002000 {
> + compatible = "mediatek,mt7629-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11002000 0 0x400>;
> + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_UART_SEL>,
> + <&pericfg CLK_PERI_UART0_PD>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + uart1: serial@11003000 {
> + compatible = "mediatek,mt7629-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11003000 0 0x400>;
> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_UART_SEL>,
> + <&pericfg CLK_PERI_UART1_PD>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + uart2: serial@11004000 {
> + compatible = "mediatek,mt7629-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11004000 0 0x400>;
> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_UART_SEL>,
> + <&pericfg CLK_PERI_UART2_PD>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + i2c: i2c@11007000 {
> + compatible = "mediatek,mt7629-i2c",
> + "mediatek,mt2712-i2c";
> + reg = <0 0x11007000 0 0x90>,
> + <0 0x11000100 0 0x80>;
> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <4>;
> + clocks = <&pericfg CLK_PERI_I2C0_PD>,
> + <&pericfg CLK_PERI_AP_DMA_PD>;
> + clock-names = "main", "dma";
> + assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + spi: spi@1100a000 {
> + compatible = "mediatek,mt7629-spi",
> + "mediatek,mt7622-spi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0 0x1100a000 0 0x100>;
> + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
> + <&topckgen CLK_TOP_SPI0_SEL>,
> + <&pericfg CLK_PERI_SPI0_PD>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + status = "disabled";
> + };
> +
> + qspi: spi@11014000 {
> + compatible = "mediatek,mt7629-nor",
> + "mediatek,mt8173-nor";
> + reg = <0 0x11014000 0 0xe0>;
> + clocks = <&pericfg CLK_PERI_FLASH_PD>,
> + <&topckgen CLK_TOP_FLASH_SEL>;
> + clock-names = "spi", "sf";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + ssusbsys: syscon@1a000000 {
> + compatible = "mediatek,mt7629-ssusbsys", "syscon";
> + reg = <0 0x1a000000 0 0x1000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + ssusb: usb@1a0c0000 {
> + compatible = "mediatek,mt7629-xhci",
> + "mediatek,mtk-xhci";
> + reg = <0 0x1a0c0000 0 0x01000>,
> + <0 0x1a0c3e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
> + <&ssusbsys CLK_SSUSB_REF_EN>,
> + <&ssusbsys CLK_SSUSB_MCU_EN>,
> + <&ssusbsys CLK_SSUSB_DMA_EN>;
> + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
> + assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
> + <&topckgen CLK_TOP_SATA_SEL>,
> + <&topckgen CLK_TOP_HIF_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
> + <&topckgen CLK_TOP_UNIVPLL2_D4>,
> + <&topckgen CLK_TOP_UNIVPLL1_D2>;
> + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
> + phys = <&u2port0 PHY_TYPE_USB2>,
> + <&u3port0 PHY_TYPE_USB3>;
> + status = "disabled";
> + };
> +
> + u3phy1: usb-phy@1a0c4000 {
> + compatible = "mediatek,generic-tphy-v1";
> + reg = <0 0x1a0c4000 0 0x300>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + u2port0: usb-phy@1a0c4300 {
> + reg = <0 0x1a0c4300 0 0x100>;
> + clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> +
> + u3port0: usb-phy@1a1c4900 {
> + reg = <0 0x1a1c4900 0 0x700>;
> + clocks = <&clk20m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> + };
> +
> + pciesys: syscon@1a100800 {
> + compatible = "mediatek,mt7629-pciesys", "syscon";
> + reg = <0 0x1a100800 0 0x1000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + pcie: pcie@1a140000 {
> + compatible = "mediatek,mt7629-pcie";
> + device_type = "pci";
> + reg = <0 0x1a140000 0 0x1000>,
> + <0 0x1a145000 0 0x1000>;
> + reg-names = "subsys", "port1";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
> + <&pciesys CLK_PCIE_P0_AHB_EN>,
> + <&pciesys CLK_PCIE_P1_AUX_EN>,
> + <&pciesys CLK_PCIE_P1_AXI_EN>,
> + <&pciesys CLK_PCIE_P1_OBFF_EN>,
> + <&pciesys CLK_PCIE_P1_PIPE_EN>;
> + clock-names = "sys_ck1", "ahb_ck1",
> + "aux_ck1", "axi_ck1",
> + "obff_ck1", "pipe_ck1";
> + assigned-clocks = <&topckgen CLK_TOP_SATA_SEL>,
> + <&topckgen CLK_TOP_AXI_SEL>,
> + <&topckgen CLK_TOP_HIF_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>,
> + <&topckgen CLK_TOP_SYSPLL1_D2>,
> + <&topckgen CLK_TOP_UNIVPLL1_D2>;
> + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
> + bus-range = <0x00 0xff>;
> + status = "disabled";
> + ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x10000000>;
> +
> + pcie@1,0 {
> + reg = <0x0800 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + ranges;
> + status = "disabled";
> +
> + num-lanes = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie_intc1 0>,
> + <0 0 0 2 &pcie_intc1 1>,
> + <0 0 0 3 &pcie_intc1 2>,
> + <0 0 0 4 &pcie_intc1 3>;
> + pcie_intc1: interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> + };
> + };
> +
> + ethsys: syscon@1b000000 {
> + compatible = "mediatek,mt7629-ethsys", "syscon";
> + reg = <0 0x1b000000 0 0x1000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + sgmiisys0: syscon@1b128000 {
> + compatible = "mediatek,mt7629-sgmiisys", "syscon";
> + reg = <0 0x1b128000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + sgmiisys1: syscon@1b130000 {
> + compatible = "mediatek,mt7629-sgmiisys", "syscon";
> + reg = <0 0x1b130000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +};
> diff --git a/include/dt-bindings/reset/mt7629-resets.h b/include/dt-bindings/reset/mt7629-resets.h
> new file mode 100644
> index 0000000..6bb8573
> --- /dev/null
> +++ b/include/dt-bindings/reset/mt7629-resets.h
> @@ -0,0 +1,71 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2019 MediaTek Inc.
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7629
> +#define _DT_BINDINGS_RESET_CONTROLLER_MT7629
> +
> +/* INFRACFG resets */
> +#define MT7629_INFRA_EMI_MPU_RST 0
> +#define MT7629_INFRA_UART5_RST 2
> +#define MT7629_INFRA_CIRQ_EINT_RST 3
> +#define MT7629_INFRA_APXGPT_RST 4
> +#define MT7629_INFRA_SCPSYS_RST 5
> +#define MT7629_INFRA_KP_RST 6
> +#define MT7629_INFRA_SPI1_RST 7
> +#define MT7629_INFRA_SPI4_RST 8
> +#define MT7629_INFRA_SYSTIMER_RST 9
> +#define MT7629_INFRA_IRRX_RST 10
> +#define MT7629_INFRA_AO_BUS_RST 16
> +#define MT7629_INFRA_EMI_RST 32
> +#define MT7629_INFRA_APMIXED_RST 35
> +#define MT7629_INFRA_MIPI_RST 36
> +#define MT7629_INFRA_TRNG_RST 37
> +#define MT7629_INFRA_SYSCIRQ_RST 38
> +#define MT7629_INFRA_MIPI_CSI_RST 39
> +#define MT7629_INFRA_GCE_FAXI_RST 40
> +#define MT7629_INFRA_I2C_SRAM_RST 41
> +#define MT7629_INFRA_IOMMU_RST 47
> +
> +/* PERICFG resets */
> +#define MT7629_PERI_UART0_SW_RST 0
> +#define MT7629_PERI_UART1_SW_RST 1
> +#define MT7629_PERI_UART2_SW_RST 2
> +#define MT7629_PERI_BTIF_SW_RST 6
> +#define MT7629_PERI_PWN_SW_RST 8
> +#define MT7629_PERI_DMA_SW_RST 11
> +#define MT7629_PERI_NFI_SW_RST 14
> +#define MT7629_PERI_I2C0_SW_RST 22
> +#define MT7629_PERI_SPI0_SW_RST 33
> +#define MT7629_PERI_SPI1_SW_RST 34
> +#define MT7629_PERI_FLASHIF_SW_RST 36
> +
> +/* PCIe Subsystem resets */
> +#define MT7629_PCIE1_CORE_RST 19
> +#define MT7629_PCIE1_MMIO_RST 20
> +#define MT7629_PCIE1_HRST 21
> +#define MT7629_PCIE1_USER_RST 22
> +#define MT7629_PCIE1_PIPE_RST 23
> +#define MT7629_PCIE0_CORE_RST 27
> +#define MT7629_PCIE0_MMIO_RST 28
> +#define MT7629_PCIE0_HRST 29
> +#define MT7629_PCIE0_USER_RST 30
> +#define MT7629_PCIE0_PIPE_RST 31
> +
> +/* SSUSB Subsystem resets */
> +#define MT7629_SSUSB_PHY_PWR_RST 3
> +#define MT7629_SSUSB_MAC_PWR_RST 4
> +
> +/* ETH Subsystem resets */
> +#define MT7629_ETHSYS_SYS_RST 0
> +#define MT7629_ETHSYS_MCM_RST 2
> +#define MT7629_ETHSYS_HSDMA_RST 5
> +#define MT7629_ETHSYS_FE_RST 6
> +#define MT7629_ETHSYS_ESW_RST 16
> +#define MT7629_ETHSYS_GMAC_RST 23
> +#define MT7629_ETHSYS_EPHY_RST 24
> +#define MT7629_ETHSYS_CRYPTO_RST 29
> +#define MT7629_ETHSYS_PPE_RST 31
> +
> +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7629 */
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2019-02-25 14:37 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
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2019-01-29 4:28 [PATCH 1/7] Revert "ARM: mediatek: add MT7623a smp bringup code" Ryder Lee
2019-01-29 4:31 ` [PATCH 2/7] dt-bindings: arm: mediatek: remove unused "mediatek,mt7623a" Ryder Lee
2019-01-29 4:31 ` [PATCH 3/7] dt-bindings: arm: mediatek: add support for MT7622 BPI-R64 and MT7629 RFB Ryder Lee
2019-02-13 20:12 ` Rob Herring
2019-01-29 4:31 ` [PATCH 4/7] dt-bindings: mediatek: update bindings for MT7629 SoC Ryder Lee
2019-02-08 12:28 ` Matthias Brugger
2019-01-29 4:31 ` [PATCH 5/7] dt-bindings: interrupt-controller: update bindings for MT7623 Ryder Lee
2019-02-07 17:11 ` Matthias Brugger
2019-02-08 9:25 ` Marc Zyngier
2019-01-29 4:31 ` [PATCH 6/7] arm: mediatek: add MT7629 smp bring up code Ryder Lee
2019-01-29 4:31 ` [PATCH 7/7] arm: dts: mediatek: add basic support for MT7629 SoC Ryder Lee
2019-02-08 12:30 ` Matthias Brugger
2019-02-25 14:37 ` Rob Herring
2019-02-07 16:47 ` [PATCH 1/7] Revert "ARM: mediatek: add MT7623a smp bringup code" Matthias Brugger
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