From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53765C00140 for ; Fri, 5 Aug 2022 09:33:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240339AbiHEJdK (ORCPT ); Fri, 5 Aug 2022 05:33:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235774AbiHEJdH (ORCPT ); Fri, 5 Aug 2022 05:33:07 -0400 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64097101CA; Fri, 5 Aug 2022 02:33:06 -0700 (PDT) Received: from [10.18.29.47] (10.18.29.47) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.9; Fri, 5 Aug 2022 17:33:03 +0800 Message-ID: <4d923b9e-61d4-b4cc-906f-cb186a16e1f4@amlogic.com> Date: Fri, 5 Aug 2022 17:33:03 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH V3 4/6] dt-bindings: clk: meson: add S4 SoC peripheral clock controller bindings Content-Language: en-US To: Krzysztof Kozlowski , , , , , , Rob Herring , Neil Armstrong , Jerome Brunet , Kevin Hilman , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Martin Blumenstingl References: <20220805085716.5635-1-yu.tu@amlogic.com> <20220805085716.5635-5-yu.tu@amlogic.com> <562043e1-83d4-d4ab-2c18-20b770b02955@linaro.org> From: Yu Tu In-Reply-To: <562043e1-83d4-d4ab-2c18-20b770b02955@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.18.29.47] X-ClientProxiedBy: mail-sh.amlogic.com (10.18.11.5) To mail-sh.amlogic.com (10.18.11.5) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Krzysztof, Thank you for your reply. On 2022/8/5 17:15, Krzysztof Kozlowski wrote: > [ EXTERNAL EMAIL ] > > On 05/08/2022 10:57, Yu Tu wrote: >> Add peripheral clock controller compatible and dt-bindings header for >> the of the S4 SoC. >> >> Signed-off-by: Yu Tu >> --- >> .../bindings/clock/amlogic,s4-clkc.yaml | 92 ++++++++++++ >> include/dt-bindings/clock/amlogic,s4-clkc.h | 131 ++++++++++++++++++ >> 2 files changed, 223 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,s4-clkc.yaml >> create mode 100644 include/dt-bindings/clock/amlogic,s4-clkc.h >> >> diff --git a/Documentation/devicetree/bindings/clock/amlogic,s4-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,s4-clkc.yaml >> new file mode 100644 >> index 000000000000..2471276afda9 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/amlogic,s4-clkc.yaml > > Filename should be based on compatible, so amlogic,s4-periphs-clkc.yaml I will correct as you suggest in the next version. > >> @@ -0,0 +1,92 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/amlogic,s4-clkc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Amlogic Meson S serials Peripheral Clock Controller Device Tree Bindings > > s/Device Tree Bindings// what's mean? > >> + >> +maintainers: >> + - Neil Armstrong >> + - Jerome Brunet >> + - Yu Tu >> + >> + >> +properties: >> + compatible: >> + const: amlogic,s4-periphs-clkc >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: input fixed pll div2 >> + - description: input fixed pll div2p5 >> + - description: input fixed pll div3 >> + - description: input fixed pll div4 >> + - description: input fixed pll div5 >> + - description: input fixed pll div7 >> + - description: input hifi pll >> + - description: input gp0 pll >> + - description: input mpll0 >> + - description: input mpll1 >> + - description: input mpll2 >> + - description: input mpll3 >> + - description: input hdmi pll >> + - description: input oscillator (usually at 24MHz) >> + >> + clock-names: >> + items: >> + - const: fclk_div2 >> + - const: fclk_div2p5 >> + - const: fclk_div3 >> + - const: fclk_div4 >> + - const: fclk_div5 >> + - const: fclk_div7 >> + - const: hifi_pll >> + - const: gp0_pll >> + - const: mpll0 >> + - const: mpll1 >> + - const: mpll2 >> + - const: mpll3 >> + - const: hdmi_pll >> + - const: xtal >> + >> + "#clock-cells": >> + const: 1 >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + - "#clock-cells" >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + clkc_periphs: periphs-clock-controller@fe000000 { >> + compatible = "amlogic,s4-periphs-clkc"; >> + reg = <0xfe000000 0x49c>; >> + clocks = <&clkc_pll 3>, >> + <&clkc_pll 13>, >> + <&clkc_pll 5>, >> + <&clkc_pll 7>, >> + <&clkc_pll 9>, >> + <&clkc_pll 11>, >> + <&clkc_pll 17>, >> + <&clkc_pll 15>, >> + <&clkc_pll 25>, >> + <&clkc_pll 27>, >> + <&clkc_pll 29>, >> + <&clkc_pll 31>, >> + <&clkc_pll 20>, >> + <&xtal>; >> + clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3", "fclk_div4", >> + "fclk_div5", "fclk_div7", "hifi_pll", "gp0_pll", >> + "mpll0", "mpll1", "mpll2", "mpll3", "hdmi_pll", "xtal"; >> + #clock-cells = <1>; >> + }; >> +... >> diff --git a/include/dt-bindings/clock/amlogic,s4-clkc.h b/include/dt-bindings/clock/amlogic,s4-clkc.h >> new file mode 100644 >> index 000000000000..d203b9bbf29e >> --- /dev/null >> +++ b/include/dt-bindings/clock/amlogic,s4-clkc.h > > Probably this should be then amlogic,s4-periphs-clkc.h I will correct as you suggest in the next version. > >> @@ -0,0 +1,131 @@ >> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ >> +/* >> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. >> + * Author: Yu Tu >> + */ >> + >> +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_CLKC_H >> +#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_CLKC_H > > Best regards, > Krzysztof > > .