From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C73FECDE30 for ; Wed, 17 Oct 2018 14:14:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EE43F21526 for ; Wed, 17 Oct 2018 14:14:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="Th1dZc8t" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EE43F21526 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727537AbeJQWKp (ORCPT ); Wed, 17 Oct 2018 18:10:45 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:19549 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727095AbeJQWKo (ORCPT ); Wed, 17 Oct 2018 18:10:44 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 17 Oct 2018 07:14:53 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 17 Oct 2018 07:14:49 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 17 Oct 2018 07:14:49 -0700 Received: from [10.26.11.110] (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 17 Oct 2018 14:14:45 +0000 Subject: Re: [PATCH v1 1/5] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 To: Dmitry Osipenko , Thierry Reding , Peter De Schrijver , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring CC: , , , References: <20180830194356.14059-1-digetx@gmail.com> <20180830194356.14059-2-digetx@gmail.com> <1448e619-35c9-0195-c68a-604d10f4dc8b@gmail.com> <3c72f573-d109-b607-b7b7-d70aea3e03df@nvidia.com> From: Jon Hunter Message-ID: <4db9c51c-0c1d-c9a2-b781-250c053e6e24@nvidia.com> Date: Wed, 17 Oct 2018 15:14:43 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL104.nvidia.com (172.18.146.11) To HQMAIL101.nvidia.com (172.20.187.10) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1539785693; bh=CC9aejudljV2x8jZp3vb5NFwwia66hc9T69F+uKWAgw=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=Th1dZc8tHWLIskzLxlIH1ul0qUlM/z/vkQyMZVLX9rvmBjkyUj6M8QloWFugcGYHo a6mYIKjHFNTbw/U3FS4IhtMaLDRgwamjnJZWQzQ6niXcU0eNBYmN+M+Nds+ZVazkDv 0eXwlsGF5x7AeME9WdEfjmsKurWuvtJPHVUOzeIoji4TpOPssGlbpYV4O9HDU2vsE5 yB4gUMmHtM1D0oEmWKBU2LX71w9s0plHTXYfKjFui3fRSKV5/SbiuDJ90Jya13saMW TrDbObfGTdr0sawni+zKowLPFPLz7DNJXrrvLtdJ013ml0v14afdURVim3PhxuRrLy 8VALw3WeaBMdg== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17/10/2018 14:46, Dmitry Osipenko wrote: > On 10/17/18 4:34 PM, Jon Hunter wrote: >> >> On 17/10/2018 14:07, Dmitry Osipenko wrote: >>> On 10/17/18 3:59 PM, Jon Hunter wrote: >>>> >>>> On 17/10/2018 13:37, Dmitry Osipenko wrote: >>>>> On 10/17/18 11:40 AM, Jon Hunter wrote: >>>>>> >>>>>> On 30/08/2018 20:43, Dmitry Osipenko wrote: >>>>>>> Add device-tree binding that describes CPU frequency-scaling hardware >>>>>>> found on NVIDIA Tegra20/30 SoC's. >>>>>>> >>>>>>> Signed-off-by: Dmitry Osipenko >>>>>>> --- >>>>>>> .../cpufreq/nvidia,tegra20-cpufreq.txt | 38 +++++++++++++++++++ >>>>>>> 1 file changed, 38 insertions(+) >>>>>>> create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt >>>>>>> >>>>>>> diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt >>>>>>> new file mode 100644 >>>>>>> index 000000000000..2c51f676e958 >>>>>>> --- /dev/null >>>>>>> +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt >>>>>>> @@ -0,0 +1,38 @@ >>>>>>> +Binding for NVIDIA Tegra20 CPUFreq >>>>>>> +================================== >>>>>>> + >>>>>>> +Required properties: >>>>>>> +- clocks: Must contain an entry for each entry in clock-names. >>>>>>> + See ../clocks/clock-bindings.txt for details. >>>>>>> +- clock-names: Must include the following entries: >>>>>>> + - pll_x: main-parent for CPU clock, must be the first entry >>>>>>> + - backup: intermediate-parent for CPU clock >>>>>>> + - cpu: the CPU clock >>>>>> >>>>>> Is it likely that 'backup' will be anything other that pll_p? If not why >>>>>> not just call it pll_p? Personally, I don't 'backup' to descriptive even >>>>>> though I can see what you mean. >>>>>> >>>>>> I can see that you want to make this flexible, but if the likelihood is >>>>>> that we will just use pll_p then I am not sure it is warranted at this >>>>>> point. >>>>> >>>>> That won't describe HW, but software. And device tree should describe HW. >>>> >>>> Hmm ... well that's my point exactly. So why call it 'backup'? Sounds >>>> like a software description to me. >>> >>> Because HW is designed the way that CPU parent need to be switched to the backup clock source while main clock changes its rate. HW also allow to select among different parents, pll_p is one of those parents. >> >> Yes that part is understood. I am just splitting hairs over the actual >> name. We do the same for tegra124 but we just call it 'pll_p'. See ... >> >> Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt > > tegra124-cpufreq choose to hardwire to the pll_p, but it could be other clocks. Technically abstracting backup clock should be more correct, but result is the same in the end. Yes and that is probably intentional as that is the configuration that has been validated. So unless we are planning to test and verify every possibility, my preference is to keep it simple. But yes the result is the same. I was simply curious of your intention here because of the other series you posted with regard to the cpu clocks. Cheers Jon -- nvpublic