From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AA6FC433F5 for ; Fri, 30 Sep 2022 10:25:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232322AbiI3KZ0 (ORCPT ); Fri, 30 Sep 2022 06:25:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231817AbiI3KU3 (ORCPT ); Fri, 30 Sep 2022 06:20:29 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53AA41EF003; Fri, 30 Sep 2022 03:19:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664533150; x=1696069150; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Yz571VKU7YjksKA9v8sPWDW0ORFXhEjVtvAEg6HxfMA=; b=bt//mXXDXnnnYBct4NOjmjN8iAofSw4RrD1effenwaMEXuJDth2jMHq8 j2XN2Fb9hFIAfVLgSRS5Phhj33OGPTsHeDPA8EDaJrfEAV9hZiW2fmi0N JMAL+iRwcUBX8l0d0UTjCtUUbcrT87J/54qpxXOmhHxRCUH1LwpG0Y88i ECVuAt6yITwo/Xj7HPvpFbDCQvjW/zqL3kzBeWAwrybHWTEf46GGBC1E2 E2vliiVdn//5XmSuVtwegj45nRQfYz2D0I2qoy0A/4prS8qBZaXoHp7vF RpUqpgoQQQ0A89KxnfJdGADTbOpM8xbrY0D77Yc6rcBlv4Gtn+Vzi22G4 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10485"; a="281870112" X-IronPort-AV: E=Sophos;i="5.93,358,1654585200"; d="scan'208";a="281870112" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2022 03:19:00 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10485"; a="726807666" X-IronPort-AV: E=Sophos;i="5.93,358,1654585200"; d="scan'208";a="726807666" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2022 03:18:59 -0700 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , erdemaktas@google.com, Sean Christopherson , Sagi Shahar , Sean Christopherson Subject: [PATCH v9 051/105] KVM: VMX: Move setting of EPT MMU masks to common VT-x code Date: Fri, 30 Sep 2022 03:17:45 -0700 Message-Id: <4de99b84bf43fef3d2c117ab464e5f62d630ac91.1664530907.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sean Christopherson EPT MMU masks are used commonly for VMX and TDX. The value needs to be initialized in common code before both VMX/TDX-specific initialization code. Signed-off-by: Sean Christopherson Signed-off-by: Isaku Yamahata --- arch/x86/kvm/vmx/main.c | 5 +++++ arch/x86/kvm/vmx/vmx.c | 4 ---- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/vmx/main.c b/arch/x86/kvm/vmx/main.c index fe927aaee114..03fc1986227b 100644 --- a/arch/x86/kvm/vmx/main.c +++ b/arch/x86/kvm/vmx/main.c @@ -4,6 +4,7 @@ #include "x86_ops.h" #include "vmx.h" #include "nested.h" +#include "mmu.h" #include "pmu.h" #include "tdx.h" @@ -26,6 +27,10 @@ static __init int vt_hardware_setup(void) enable_tdx = enable_tdx && !tdx_hardware_setup(&vt_x86_ops); + if (enable_ept) + kvm_mmu_set_ept_masks(enable_ept_ad_bits, + cpu_has_vmx_ept_execute_only()); + return 0; } diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index ec1570b151f5..d78f37e2e2af 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -8259,10 +8259,6 @@ __init int vmx_hardware_setup(void) set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ - if (enable_ept) - kvm_mmu_set_ept_masks(enable_ept_ad_bits, - cpu_has_vmx_ept_execute_only()); - /* * Setup shadow_me_value/shadow_me_mask to include MKTME KeyID * bits to shadow_zero_check. -- 2.25.1