From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71F92C04AB6 for ; Fri, 31 May 2019 20:13:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 471DB24647 for ; Fri, 31 May 2019 20:13:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727509AbfEaUNT (ORCPT ); Fri, 31 May 2019 16:13:19 -0400 Received: from mga03.intel.com ([134.134.136.65]:57998 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727316AbfEaUNT (ORCPT ); Fri, 31 May 2019 16:13:19 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 May 2019 13:13:18 -0700 X-ExtLoop1: 1 Received: from ray.jf.intel.com (HELO [10.7.198.156]) ([10.7.198.156]) by orsmga008.jf.intel.com with ESMTP; 31 May 2019 13:13:17 -0700 Subject: Re: [RFC PATCH v2 11/12] x86/mm/tlb: Use async and inline messages for flushing To: Nadav Amit , Andy Lutomirski Cc: Peter Zijlstra , Andy Lutomirski , Borislav Petkov , Ingo Molnar , Thomas Gleixner , "x86@kernel.org" , "linux-kernel@vger.kernel.org" , Dave Hansen References: <20190531063645.4697-1-namit@vmware.com> <20190531063645.4697-12-namit@vmware.com> <20190531105758.GO2623@hirez.programming.kicks-ass.net> <16D8E001-98A0-4ABC-AFE8-0F230B869027@amacapital.net> <82DB7035-D7BE-4D79-BBC0-B271FB4BF740@vmware.com> From: Dave Hansen Openpgp: preference=signencrypt Autocrypt: addr=dave.hansen@intel.com; keydata= mQINBE6HMP0BEADIMA3XYkQfF3dwHlj58Yjsc4E5y5G67cfbt8dvaUq2fx1lR0K9h1bOI6fC oAiUXvGAOxPDsB/P6UEOISPpLl5IuYsSwAeZGkdQ5g6m1xq7AlDJQZddhr/1DC/nMVa/2BoY 2UnKuZuSBu7lgOE193+7Uks3416N2hTkyKUSNkduyoZ9F5twiBhxPJwPtn/wnch6n5RsoXsb ygOEDxLEsSk/7eyFycjE+btUtAWZtx+HseyaGfqkZK0Z9bT1lsaHecmB203xShwCPT49Blxz VOab8668QpaEOdLGhtvrVYVK7x4skyT3nGWcgDCl5/Vp3TWA4K+IofwvXzX2ON/Mj7aQwf5W iC+3nWC7q0uxKwwsddJ0Nu+dpA/UORQWa1NiAftEoSpk5+nUUi0WE+5DRm0H+TXKBWMGNCFn c6+EKg5zQaa8KqymHcOrSXNPmzJuXvDQ8uj2J8XuzCZfK4uy1+YdIr0yyEMI7mdh4KX50LO1 pmowEqDh7dLShTOif/7UtQYrzYq9cPnjU2ZW4qd5Qz2joSGTG9eCXLz5PRe5SqHxv6ljk8mb ApNuY7bOXO/A7T2j5RwXIlcmssqIjBcxsRRoIbpCwWWGjkYjzYCjgsNFL6rt4OL11OUF37wL QcTl7fbCGv53KfKPdYD5hcbguLKi/aCccJK18ZwNjFhqr4MliQARAQABtEVEYXZpZCBDaHJp c3RvcGhlciBIYW5zZW4gKEludGVsIFdvcmsgQWRkcmVzcykgPGRhdmUuaGFuc2VuQGludGVs LmNvbT6JAjgEEwECACIFAlQ+9J0CGwMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheAAAoJEGg1 lTBwyZKwLZUP/0dnbhDc229u2u6WtK1s1cSd9WsflGXGagkR6liJ4um3XCfYWDHvIdkHYC1t MNcVHFBwmQkawxsYvgO8kXT3SaFZe4ISfB4K4CL2qp4JO+nJdlFUbZI7cz/Td9z8nHjMcWYF IQuTsWOLs/LBMTs+ANumibtw6UkiGVD3dfHJAOPNApjVr+M0P/lVmTeP8w0uVcd2syiaU5jB aht9CYATn+ytFGWZnBEEQFnqcibIaOrmoBLu2b3fKJEd8Jp7NHDSIdrvrMjYynmc6sZKUqH2 I1qOevaa8jUg7wlLJAWGfIqnu85kkqrVOkbNbk4TPub7VOqA6qG5GCNEIv6ZY7HLYd/vAkVY E8Plzq/NwLAuOWxvGrOl7OPuwVeR4hBDfcrNb990MFPpjGgACzAZyjdmYoMu8j3/MAEW4P0z F5+EYJAOZ+z212y1pchNNauehORXgjrNKsZwxwKpPY9qb84E3O9KYpwfATsqOoQ6tTgr+1BR CCwP712H+E9U5HJ0iibN/CDZFVPL1bRerHziuwuQuvE0qWg0+0SChFe9oq0KAwEkVs6ZDMB2 P16MieEEQ6StQRlvy2YBv80L1TMl3T90Bo1UUn6ARXEpcbFE0/aORH/jEXcRteb+vuik5UGY 5TsyLYdPur3TXm7XDBdmmyQVJjnJKYK9AQxj95KlXLVO38lcuQINBFRjzmoBEACyAxbvUEhd GDGNg0JhDdezyTdN8C9BFsdxyTLnSH31NRiyp1QtuxvcqGZjb2trDVuCbIzRrgMZLVgo3upr MIOx1CXEgmn23Zhh0EpdVHM8IKx9Z7V0r+rrpRWFE8/wQZngKYVi49PGoZj50ZEifEJ5qn/H Nsp2+Y+bTUjDdgWMATg9DiFMyv8fvoqgNsNyrrZTnSgoLzdxr89FGHZCoSoAK8gfgFHuO54B lI8QOfPDG9WDPJ66HCodjTlBEr/Cwq6GruxS5i2Y33YVqxvFvDa1tUtl+iJ2SWKS9kCai2DR 3BwVONJEYSDQaven/EHMlY1q8Vln3lGPsS11vSUK3QcNJjmrgYxH5KsVsf6PNRj9mp8Z1kIG qjRx08+nnyStWC0gZH6NrYyS9rpqH3j+hA2WcI7De51L4Rv9pFwzp161mvtc6eC/GxaiUGuH BNAVP0PY0fqvIC68p3rLIAW3f97uv4ce2RSQ7LbsPsimOeCo/5vgS6YQsj83E+AipPr09Caj 0hloj+hFoqiticNpmsxdWKoOsV0PftcQvBCCYuhKbZV9s5hjt9qn8CE86A5g5KqDf83Fxqm/ vXKgHNFHE5zgXGZnrmaf6resQzbvJHO0Fb0CcIohzrpPaL3YepcLDoCCgElGMGQjdCcSQ+Ci FCRl0Bvyj1YZUql+ZkptgGjikQARAQABiQIfBBgBAgAJBQJUY85qAhsMAAoJEGg1lTBwyZKw l4IQAIKHs/9po4spZDFyfDjunimEhVHqlUt7ggR1Hsl/tkvTSze8pI1P6dGp2XW6AnH1iayn yRcoyT0ZJ+Zmm4xAH1zqKjWplzqdb/dO28qk0bPso8+1oPO8oDhLm1+tY+cOvufXkBTm+whm +AyNTjaCRt6aSMnA/QHVGSJ8grrTJCoACVNhnXg/R0g90g8iV8Q+IBZyDkG0tBThaDdw1B2l asInUTeb9EiVfL/Zjdg5VWiF9LL7iS+9hTeVdR09vThQ/DhVbCNxVk+DtyBHsjOKifrVsYep WpRGBIAu3bK8eXtyvrw1igWTNs2wazJ71+0z2jMzbclKAyRHKU9JdN6Hkkgr2nPb561yjcB8 sIq1pFXKyO+nKy6SZYxOvHxCcjk2fkw6UmPU6/j/nQlj2lfOAgNVKuDLothIxzi8pndB8Jju KktE5HJqUUMXePkAYIxEQ0mMc8Po7tuXdejgPMwgP7x65xtfEqI0RuzbUioFltsp1jUaRwQZ MTsCeQDdjpgHsj+P2ZDeEKCbma4m6Ez/YWs4+zDm1X8uZDkZcfQlD9NldbKDJEXLIjYWo1PH hYepSffIWPyvBMBTW2W5FRjJ4vLRrJSUoEfJuPQ3vW9Y73foyo/qFoURHO48AinGPZ7PC7TF vUaNOTjKedrqHkaOcqB185ahG2had0xnFsDPlx5y Message-ID: <4e0ed5a5-0e5e-3481-e646-3f032f17ac60@intel.com> Date: Fri, 31 May 2019 13:13:09 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <82DB7035-D7BE-4D79-BBC0-B271FB4BF740@vmware.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/31/19 12:31 PM, Nadav Amit wrote: >> On May 31, 2019, at 11:44 AM, Andy Lutomirski wrote: >> >> >> >>> On May 31, 2019, at 3:57 AM, Peter Zijlstra wrote: >>> >>>> On Thu, May 30, 2019 at 11:36:44PM -0700, Nadav Amit wrote: >>>> When we flush userspace mappings, we can defer the TLB flushes, as long >>>> the following conditions are met: >>>> >>>> 1. No tables are freed, since otherwise speculative page walks might >>>> cause machine-checks. >>>> >>>> 2. No one would access userspace before flush takes place. Specifically, >>>> NMI handlers and kprobes would avoid accessing userspace. >>>> >>>> Use the new SMP support to execute remote function calls with inlined >>>> data for the matter. The function remote TLB flushing function would be >>>> executed asynchronously and the local CPU would continue execution as >>>> soon as the IPI was delivered, before the function was actually >>>> executed. Since tlb_flush_info is copied, there is no risk it would >>>> change before the TLB flush is actually executed. >>>> >>>> Change nmi_uaccess_okay() to check whether a remote TLB flush is >>>> currently in progress on this CPU by checking whether the asynchronously >>>> called function is the remote TLB flushing function. The current >>>> implementation disallows access in such cases, but it is also possible >>>> to flush the entire TLB in such case and allow access. >>> >>> ARGGH, brain hurt. I'm not sure I fully understand this one. How is it >>> different from today, where the NMI can hit in the middle of the TLB >>> invalidation? >>> >>> Also; since we're not waiting on the IPI, what prevents us from freeing >>> the user pages before the remote CPU is 'done' with them? Currently the >>> synchronous IPI is like a sync point where we *know* the remote CPU is >>> completely done accessing the page. >>> >>> Where getting an IPI stops speculation, speculation again restarts >>> inside the interrupt handler, and until we've passed the INVLPG/MOV CR3, >>> speculation can happen on that TLB entry, even though we've already >>> freed and re-used the user-page. >>> >>> Also, what happens if the TLB invalidation IPI is stuck behind another >>> smp_function_call IPI that is doing user-access? >>> >>> As said,.. brain hurts. >> >> Speculation aside, any code doing dirty tracking needs the flush to happen >> for real before it reads the dirty bit. >> >> How does this patch guarantee that the flush is really done before someone >> depends on it? > > I was always under the impression that the dirty-bit is pass-through - the > A/D-assist walks the tables and sets the dirty bit upon access. Otherwise, > what happens when you invalidate the PTE, and have already marked the PTE as > non-present? Would the CPU set the dirty-bit at this point? Modulo bugs^Werrata... No. What actually happens is that a try-to-set-dirty-bit page table walk acts just like a TLB miss. The old contents of the TLB are discarded and only the in-memory contents matter for forward progress. If Present=0 when the PTE is reached, you'll get a normal Present=0 page fault. > In this regard, I remember this thread of Dave Hansen [1], which also seems > to me as supporting the notion the dirty-bit is set on write and not on > INVLPG. ... and that's the erratum I was hoping you wouldn't mention. :) But, yeah, I don't think it's possible to set the Dirty bit on INVLPG. The bits are set on establishing TLB entries, not on evicting or flushing them. I hope that clears it up.