Re: [PATCH v1 1/6] clk: divider: Implement and wire up .determine_rate by default

[Alex Bee <knaerzche@gmail.com>]

Hi,

Am 03.07.21 um 00:51 schrieb Martin Blumenstingl:
> .determine_rate is meant to replace .round_rate. The former comes with a
> benefit which is especially relevant on 32-bit systems: since
> .determine_rate uses an "unsigned long" (compared to a "signed long"
> which is used by .round_rate) the maximum value on 32-bit systems
> increases from 2^31 (or approx. 2.14GHz) to 2^32 (or approx. 4.29GHz).
>
> Implement .determine_rate in addition to .round_rate so drivers that are
> using clk_divider_{ro_,}ops can benefit from this by default. Keep the
> .round_rate callback for now since some drivers rely on
> clk_divider_ops.round_rate being implemented.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
This commit  breaks composite clocks with multiple parents, since it 
adds a  determine_rate callback, which is preferred over 
clock_round_rate in  clk_composite_determine_rate in clk-composite.c and 
the "best-parent"-determination  is only done for clock_round_rate-op 
there.
There is no "best-parent"-determination  in determine_rate in 
clk-divider which clk-compsite seems to expect - nor any multiple 
parents handling at all.  That means that the composite will always stay 
at the same/initial parent  clock (from the mux), without ever changing 
it (even if necessary).

This breaks lot of clocks for Rockchip which intensively uses 
composites,  i.e. those clocks will always stay at the initial parent, 
which in some cases  is the XTAL clock and I strongly guess it is the 
same for other platforms,  which use composite clocks having more than 
one parent (e.g. mediatek, ti ...)

Example (RK3399)
clk_sdio is set (initialized) with XTAL (24 MHz) as parent in u-boot.  
It will always stay at this parent, even if the mmc driver sets a rate 
of  200 MHz (fails, as the nature of things), which should switch it to 
any of its possible parent PLLs defined in 
mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p (see clk-rk3399.c)  - which 
never happens.

Reverting this commit makes it work again: Unless there is a quick and 
obvious fix for that, I guess this should be done for 5.15 - even if the 
real issue is somewhere else.

Alex

> ---
>   drivers/clk/clk-divider.c | 23 +++++++++++++++++++++++
>   1 file changed, 23 insertions(+)
>
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index 87ba4966b0e8..f6b2bf558486 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -446,6 +446,27 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
>   				  divider->width, divider->flags);
>   }
>   
> +static int clk_divider_determine_rate(struct clk_hw *hw,
> +				      struct clk_rate_request *req)
> +{
> +	struct clk_divider *divider = to_clk_divider(hw);
> +
> +	/* if read only, just return current value */
> +	if (divider->flags & CLK_DIVIDER_READ_ONLY) {
> +		u32 val;
> +
> +		val = clk_div_readl(divider) >> divider->shift;
> +		val &= clk_div_mask(divider->width);
> +
> +		return divider_ro_determine_rate(hw, req, divider->table,
> +						 divider->width,
> +						 divider->flags, val);
> +	}
> +
> +	return divider_determine_rate(hw, req, divider->table, divider->width,
> +				      divider->flags);
> +}
> +
>   int divider_get_val(unsigned long rate, unsigned long parent_rate,
>   		    const struct clk_div_table *table, u8 width,
>   		    unsigned long flags)
> @@ -501,6 +522,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
>   const struct clk_ops clk_divider_ops = {
>   	.recalc_rate = clk_divider_recalc_rate,
>   	.round_rate = clk_divider_round_rate,
> +	.determine_rate = clk_divider_determine_rate,
>   	.set_rate = clk_divider_set_rate,
>   };
>   EXPORT_SYMBOL_GPL(clk_divider_ops);
> @@ -508,6 +530,7 @@ EXPORT_SYMBOL_GPL(clk_divider_ops);
>   const struct clk_ops clk_divider_ro_ops = {
>   	.recalc_rate = clk_divider_recalc_rate,
>   	.round_rate = clk_divider_round_rate,
> +	.determine_rate = clk_divider_determine_rate,
>   };
>   EXPORT_SYMBOL_GPL(clk_divider_ro_ops);
>