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From: "Derrick, Jonathan" <jonathan.derrick@intel.com>
To: "sathyanarayanan.kuppuswamy@linux.intel.com" 
	<sathyanarayanan.kuppuswamy@linux.intel.com>,
	"helgaas@kernel.org" <helgaas@kernel.org>
Cc: "rajatja@google.com" <rajatja@google.com>,
	"kbusch@kernel.org" <kbusch@kernel.org>,
	"ruscur@russell.cc" <ruscur@russell.cc>,
	"fred@fredlawl.com" <fred@fredlawl.com>,
	"Wysocki, Rafael J" <rafael.j.wysocki@intel.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"alex.williamson@redhat.com" <alex.williamson@redhat.com>,
	"sbobroff@linux.ibm.com" <sbobroff@linux.ibm.com>,
	"olof@lixom.net" <olof@lixom.net>,
	"oohall@gmail.com" <oohall@gmail.com>,
	"mika.westerberg@linux.intel.com"
	<mika.westerberg@linux.intel.com>,
	"linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"Patel, Mayurkumar" <mayurkumar.patel@intel.com>,
	"andriy.shevchenko@linux.intel.com" 
	<andriy.shevchenko@linux.intel.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>
Subject: Re: [PATCH v2 1/2] PCI/AER: Allow Native AER Host Bridges to use AER
Date: Thu, 23 Apr 2020 15:11:06 +0000	[thread overview]
Message-ID: <4f044eca9f9f4cfc413c850046112b870e85e8d7.camel@intel.com> (raw)
In-Reply-To: <9f8c2a62-e67d-2869-db11-4644b69815f4@linux.intel.com>

Hi Sathyanarayanan,

On Wed, 2020-04-22 at 15:48 -0700, Kuppuswamy, Sathyanarayanan wrote:
> 
> On 4/20/20 2:37 PM, Jon Derrick wrote:
> > Some platforms have a mix of ports whose capabilities can be negotiated
> > by _OSC, and some ports which are not described by ACPI and instead
> > managed by Native drivers. The existing Firmware-First HEST model can
> > incorrectly tag these Native, Non-ACPI ports as Firmware-First managed
> > ports by advertising the HEST Global Flag and matching the type and
> > class of the port (aer_hest_parse).
> Is there a real use case for mixed mode (one host bridge in FF mode and
> another in native)?

Intel's VMD exposes PCIe segments containing Root Ports and Bridges and
other DPC consumers. These extra PCIe domains aren't described by ACPI.
There have been a few versions where DPC won't bind due to platform's
HEST configuration.

> > If the port requests Native AER through the Host Bridge's capability
> > settings, the AER driver should honor those settings and allow the port
> > to bind. This patch changes the definition of Firmware-First to exclude
> > ports whose Host Bridges request Native AER.
> > 
> > Signed-off-by: Jon Derrick <jonathan.derrick@intel.com>
> > ---
> >   drivers/pci/pcie/aer.c | 3 +++
> >   1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
> > index f4274d3..30fbd1f 100644
> > --- a/drivers/pci/pcie/aer.c
> > +++ b/drivers/pci/pcie/aer.c
> > @@ -314,6 +314,9 @@ int pcie_aer_get_firmware_first(struct pci_dev *dev)
> >   	if (pcie_ports_native)
> >   		return 0;
> >   
> > +	if (pci_find_host_bridge(dev->bus)->native_aer)
> > +		return 0;
> > +
> >   	if (!dev->__aer_firmware_first_valid)
> >   		aer_set_firmware_first(dev);
> >   	return dev->__aer_firmware_first;
> > 

  reply	other threads:[~2020-04-23 15:11 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-20 21:37 [PATCH v2 0/2] Honoring Native AER/DPC Host Bridges Jon Derrick
2020-04-20 21:37 ` [PATCH v2 1/2] PCI/AER: Allow Native AER Host Bridges to use AER Jon Derrick
2020-04-22 22:48   ` Kuppuswamy, Sathyanarayanan
2020-04-23 15:11     ` Derrick, Jonathan [this message]
2020-04-24 23:30   ` Bjorn Helgaas
2020-04-27 16:11     ` Derrick, Jonathan
2020-04-27 22:14       ` Bjorn Helgaas
2020-04-20 21:37 ` [PATCH v2 2/2] PCI/DPC: Allow Native DPC Host Bridges to use DPC Jon Derrick
2020-04-22 22:50   ` Kuppuswamy, Sathyanarayanan
2020-04-23 15:11     ` Derrick, Jonathan
2020-04-25 20:46       ` Kuppuswamy, Sathyanarayanan
2020-04-27 15:15         ` Derrick, Jonathan
2020-04-27 15:43           ` Kuppuswamy, Sathyanarayanan

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