From: Vidya Sagar <vidyas@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: <bhelgaas@google.com>, <robh+dt@kernel.org>,
<mark.rutland@arm.com>, <jonathanh@nvidia.com>, <kishon@ti.com>,
<catalin.marinas@arm.com>, <will.deacon@arm.com>,
<lorenzo.pieralisi@arm.com>, <jingoohan1@gmail.com>,
<gustavo.pimentel@synopsys.com>, <mperttunen@nvidia.com>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
<mmaddireddy@nvidia.com>, <sagar.tv@gmail.com>
Subject: Re: [PATCH V2 01/16] PCI: Add #defines for PCIe spec r4.0 features
Date: Tue, 16 Apr 2019 18:45:14 +0530 [thread overview]
Message-ID: <4f672035-262b-1e53-2718-8c0c5612b3f3@nvidia.com> (raw)
In-Reply-To: <20190411101353.GE4633@ulmo>
On 4/11/2019 3:43 PM, Thierry Reding wrote:
> On Fri, Apr 05, 2019 at 01:24:28AM +0530, Vidya Sagar wrote:
>> Add #defines for the Data Link Feature and Physical Layer 16.0 GT/s
>> features.
>>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> ---
>> Changes from [v1]:
>> * None
>>
>> include/uapi/linux/pci_regs.h | 22 +++++++++++++++++++++-
>> 1 file changed, 21 insertions(+), 1 deletion(-)
>>
>> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
>> index 5c98133f2c94..3e01b55d548d 100644
>> --- a/include/uapi/linux/pci_regs.h
>> +++ b/include/uapi/linux/pci_regs.h
>> @@ -705,7 +705,9 @@
>> #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
>> #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
>> #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
>> -#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
>> +#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */
>> +#define PCI_EXT_CAP_ID_PL 0x26 /* Physical Layer 16.0 GT/s */
>> +#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL
>>
>> #define PCI_EXT_CAP_DSN_SIZEOF 12
>> #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
>> @@ -1045,4 +1047,22 @@
>> #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */
>> #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */
>>
>> +/* Data Link Feature */
>> +#define PCI_DLF_CAP 0x04 /* Capabilities Register */
>> +#define PCI_DLF_LOCAL_DLF_SUP_MASK 0x007fffff /* Local Data Link Feature Supported */
>> +#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */
>> +#define PCI_DLF_STS 0x08 /* Status Register */
>> +#define PCI_DLF_REMOTE_DLF_SUP_MASK 0x007fffff /* Remote Data Link Feature Supported */
>> +#define PCI_DLF_REMOTE_DLF_SUP_VALID 0x80000000 /* Remote Data Link Feature Support Valid */
>> +
>> +/* Physical Layer 16.0 GT/s */
>> +#define PCI_PL_16GT_CAP 0x04 /* Capabilities Register */
>> +#define PCI_PL_16GT_CTRL 0x08 /* Control Register */
>> +#define PCI_PL_16GT_STS 0x0c /* Status Register */
>> +#define PCI_PL_16GT_LDPM_STS 0x10 /* Local Data Parity Mismatch Status Register */
>> +#define PCI_PL_16GT_FRDPM_STS 0x14 /* First Retimer Data Parity Mismatch Status Register */
>> +#define PCI_PL_16GT_SRDPM_STS 0x18 /* Second Retimer Data Parity Mismatch Status Register */
>> +#define PCI_PL_16GT_RSVD 0x1C /* Reserved */
>> +#define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */
>
> This looks correct comparing to the specification. However, this leaves
> out some definitions, so I'm wondering if perhaps this should include
> all field definitions. There are also extended capabilities between the
> current maximum 0x1F and 0x25. Perhaps those should be added as well. I
> guess this could always be done as a follow-up.
>
> Perhaps it'd be better to change the subject to more accurately reflect
> that you're only adding a couple of PCIe 4.0 features.
I'll change subject accordingly.
>
> Other than that:
>
> Reviewed-by: Thierry Reding <treding@nvidia.com>
>
next prev parent reply other threads:[~2019-04-16 13:15 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-04 19:54 [PATCH V2 00/16] Add Tegra194 PCIe support Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 01/16] PCI: Add #defines for PCIe spec r4.0 features Vidya Sagar
2019-04-11 10:13 ` Thierry Reding
2019-04-16 13:15 ` Vidya Sagar [this message]
2019-04-04 19:54 ` [PATCH V2 02/16] PCI/PME: Export pcie_pme_disable_msi() API Vidya Sagar
2019-04-11 10:16 ` Thierry Reding
2019-04-16 13:30 ` Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 03/16] PCI: Export pcie_bus_config symbol Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 04/16] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 05/16] PCI: dwc: Move config space capability search API Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 06/16] PCI: dwc: Add ext " Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 07/16] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-04-15 14:54 ` Thierry Reding
2019-04-16 14:29 ` Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 08/16] PCI: dwc: Add support to enable " Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 09/16] Documentation/devicetree: Add PCIe supports-clkreq property Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 10/16] dt-bindings: PCI: tegra: Add device tree support for T194 Vidya Sagar
2019-04-15 15:08 ` Thierry Reding
2019-04-16 15:33 ` Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 11/16] dt-bindings: PHY: P2U: Add Tegra 194 P2U block Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 12/16] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT Vidya Sagar
2019-04-15 15:15 ` Thierry Reding
2019-04-16 17:48 ` Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 13/16] arm64: tegra: Enable PCIe slots in P2972-0000 board Vidya Sagar
2019-04-15 15:12 ` Thierry Reding
2019-04-16 17:55 ` Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 14/16] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-04-15 15:31 ` Thierry Reding
2019-04-15 15:33 ` Thierry Reding
2019-04-16 18:14 ` Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 15/16] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 16/16] arm64: Add Tegra194 PCIe driver to defconfig Vidya Sagar
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