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From: "Liang, Kan" <kan.liang@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: acme@kernel.org, mingo@redhat.com, linux-kernel@vger.kernel.org,
	tglx@linutronix.de, jolsa@kernel.org, eranian@google.com,
	alexander.shishkin@linux.intel.com, ak@linux.intel.com
Subject: Re: [PATCH V5 08/12] perf/x86/intel: Add Icelake support
Date: Mon, 8 Apr 2019 11:45:59 -0400	[thread overview]
Message-ID: <4ff8fec9-fb41-b11d-b7ed-4c716b558adc@linux.intel.com> (raw)
In-Reply-To: <20190408150654.GV12232@hirez.programming.kicks-ass.net>



On 4/8/2019 11:06 AM, Peter Zijlstra wrote:
> On Tue, Apr 02, 2019 at 12:45:05PM -0700, kan.liang@linux.intel.com wrote:
>> +static struct event_constraint *
>> +icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
>> +			  struct perf_event *event)
>> +{
>> +	/*
>> +	 * Fixed counter 0 has less skid.
>> +	 * Force instruction:ppp in Fixed counter 0
>> +	 */
>> +	if ((event->attr.precise_ip == 3) &&
>> +	    ((event->hw.config & X86_RAW_EVENT_MASK) == 0x00c0))
>> +		return &fixed_counter0_constraint;
> 
> Does that want to be:
> 
> 		event->hw.config == X86_CONFIG(.event=0xc0)
> 
> ?
> 
> That is, are there really bits we want to mask in there?

For instruction event, right, we don't need mask it.
I will change it.

Thanks,
Kan

> 
>> +
>> +	return hsw_get_event_constraints(cpuc, idx, event);
>> +}

  reply	other threads:[~2019-04-08 15:46 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-02 19:44 [PATCH V5 00/12] perf: Add Icelake support (kernel only, except Topdown) kan.liang
2019-04-02 19:44 ` [PATCH V5 01/12] perf/x86: Fix wrong PEBS_REGS kan.liang
2019-04-16 11:32   ` [tip:perf/core] perf/x86: Fix incorrect PEBS_REGS tip-bot for Kan Liang
2019-04-02 19:44 ` [PATCH V5 02/12] perf/x86: Support outputting XMM registers kan.liang
2019-04-16 11:34   ` [tip:perf/core] " tip-bot for Kan Liang
2019-04-02 19:45 ` [PATCH V5 03/12] perf/x86/intel: Extract memory code PEBS parser for reuse kan.liang
2019-04-16 11:35   ` [tip:perf/core] " tip-bot for Andi Kleen
2019-04-02 19:45 ` [PATCH V5 04/12] perf/x86/intel/ds: Extract code of event update in short period kan.liang
2019-04-16 11:35   ` [tip:perf/core] " tip-bot for Kan Liang
2019-04-02 19:45 ` [PATCH V5 05/12] perf/x86/intel: Support adaptive PEBSv4 kan.liang
2019-04-08 14:55   ` Peter Zijlstra
2019-04-16 11:36   ` [tip:perf/core] perf/x86/intel: Support adaptive PEBS v4 tip-bot for Kan Liang
2019-04-02 19:45 ` [PATCH V5 06/12] perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles them kan.liang
2019-04-16 11:37   ` [tip:perf/core] " tip-bot for Andi Kleen
2019-04-02 19:45 ` [PATCH V5 07/12] perf/x86: Support constraint ranges kan.liang
2019-04-16 11:37   ` [tip:perf/core] " tip-bot for Peter Zijlstra
2019-04-02 19:45 ` [PATCH V5 08/12] perf/x86/intel: Add Icelake support kan.liang
2019-04-08 15:06   ` Peter Zijlstra
2019-04-08 15:45     ` Liang, Kan [this message]
2019-04-10 18:22       ` Liang, Kan
2019-04-10 19:47         ` Peter Zijlstra
2019-04-11  9:00           ` Peter Zijlstra
2019-04-11 13:29             ` Liang, Kan
2019-04-16 11:38   ` [tip:perf/core] " tip-bot for Kan Liang
2019-04-02 19:45 ` [PATCH V5 09/12] perf/x86/intel/cstate: " kan.liang
2019-04-16 11:39   ` [tip:perf/core] " tip-bot for Kan Liang
2019-04-02 19:45 ` [PATCH V5 10/12] perf/x86/intel/rapl: " kan.liang
2019-04-16 11:39   ` [tip:perf/core] " tip-bot for Kan Liang
2019-04-02 19:45 ` [PATCH V5 11/12] perf/x86/msr: " kan.liang
2019-04-16 11:40   ` [tip:perf/core] " tip-bot for Kan Liang
2019-04-02 19:45 ` [PATCH V5 12/12] perf/x86/intel/uncore: Add Intel Icelake uncore support kan.liang
2019-04-16 11:40   ` [tip:perf/core] " tip-bot for Kan Liang
2019-04-08 15:41 ` [PATCH V5 00/12] perf: Add Icelake support (kernel only, except Topdown) Peter Zijlstra
2019-04-08 16:06   ` Liang, Kan
2019-04-08 16:25     ` Liang, Kan
2019-04-08 16:28       ` Peter Zijlstra
2019-04-08 22:49     ` Liang, Kan

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