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Wed, 31 Jul 2019 04:32:23 -0700 Received: from [172.30.17.116] by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1hsmq9-0000z5-C2; Wed, 31 Jul 2019 04:32:17 -0700 Subject: Re: mmc: sdhci-of-arasan small issue with clock with 5.2 kernel To: Paul Thomas , Michal Simek , Adrian Hunter , Ulf Hansson , linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel , Manish Narani References: From: Michal Simek Message-ID: <505526dc-5b3c-eb7d-a619-195d0b6dce81@xilinx.com> Date: Wed, 31 Jul 2019 13:32:15 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(376002)(396003)(39860400002)(136003)(346002)(2980300002)(189003)(199004)(9786002)(8676002)(44832011)(106002)(65956001)(36756003)(230700001)(47776003)(6306002)(58126008)(316002)(65806001)(8936002)(70586007)(81156014)(110136005)(70206006)(229853002)(5660300002)(81166006)(50466002)(76176011)(64126003)(966005)(126002)(6636002)(31686004)(336012)(305945005)(2486003)(52146003)(23676004)(31696002)(186003)(426003)(36386004)(2906002)(476003)(11346002)(65826007)(14444005)(486006)(446003)(2616005)(26005)(478600001)(6246003)(63266004)(356004);DIR:OUT;SFP:1101;SCL:1;SRVR:BY5PR02MB6737;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b305cc29-bc07-4d01-af95-08d715aac557 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(4709080)(1401327)(2017052603328);SRVR:BY5PR02MB6737; X-MS-TrafficTypeDiagnostic: BY5PR02MB6737: X-MS-Exchange-PUrlCount: 3 X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-Forefront-PRVS: 011579F31F X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: zbwoBjW9bzNzMF70CImbYRfQs9Eq7USzcT0cq2WaYWl4MxxBsGTaoiGI5ucwu5xnNP5Y1wLwjPUYLxtg1OQ/CMmUBDF9maeVAKMPsS2nbyx/VnVoT7m8cSdE+a7e4wnKxzdoQvSpBeTCc2Mm/Md5rb80DEPQQf7apxxfnoQ4vZW3yZObU0WvCEaAcYRKGKZQbUzOQ2w+J8jPQoVaU2+lv46pTHAoCsv6Dd8qGavTs/3VzE9wJii/JN0ePiGg7HuuPwHILZhB84fM39QNV/1GkT8CDeIGzfWToqeqjhj9Nl2wk3MUn5zB6Co/zagNans6Q2d4lrRnVvSA9L5No8/meEZbdK0gFh8ZFBxkbTmBahrSl3KMUUdn4GL98LcQ7+U79Q140/mgucljP+2H2UzuAJ/Oa9zdbwRzdfInRVIZqx8= X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Jul 2019 11:32:29.2321 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b305cc29-bc07-4d01-af95-08d715aac557 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR02MB6737 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org +Manish, On 26. 07. 19 20:23, Paul Thomas wrote: > Hello, > > I'm using the arm64 Zynq Ultrascale+ parts, and I'm running into what > I think is a small issue in sdhci-of-arasan with the handling of the > 'clk_xin' which becomes pltfm_host->clk. > > If I just use the mainline zynqmp-clk.dtsi file then 'clk_xin' get's > blindly defined as a "fixed-clock" at 200 Mhz and everything seems to > work fine. > > However, in this design the clock is actually 50 Mhz [1]. For other > reasons [2] I switched the device-tree clock definitions to actually > use the zynqmp firmware interface for getting the clocks [3] when I do > this the clock is then correctly detected as 50 MHz: > # cat /sys/kernel/debug/clk/clk_summary > ... > sdio0_ref 1 1 1 50000000 0 0 50000 > ... > > And this is the frequency that is given to the controller (I put > printk's in to verify that 200 and 50 were the respective values for > mhz): > https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/mmc/host/sdhci-of-arasan.c?h=v5.2.3#n594 > > At this point the functionality becomes partially broken. Detecting > the chip and some reads seem to work, but then when I go to fdisk > write there are errors such as: > [ 56.481985] 002: print_req_error: I/O error, dev mmcblk0, sector 0 flags 1 > [ 56.481999] 002: Buffer I/O error on dev mmcblk0, logical block 0, > lost async page write > > It seems to me that giving the real 'clk_xin' frequency to the > controller should not break anything? For now I'm fine with just using > the incorrect 200 MHz fixed-clock, but I thought someone might be > interested in this. > > This controller is connected to an eMMC part. > > I did try reducing spi-max-frequency from 10M down to 1M, but that > does not seem to make a difference. > > thanks, > Paul > > [1] As defined in Vivado in the MPSoC block in Output Clocks -> Low > Power Domain Clocks -> Peripherals/IO Clocks -> SDIO0 > [2] To enable the macb driver to properly set the frequency of the GEM > clock so that 100 Mb/s works > [3] The device-tree like this: > https://github.com/Xilinx/linux-xlnx/blob/master/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi > and adding "xlnx,zynqmp-clk" clock-controller > It should be related to tap delay setup which Manish sent to mainline for review some time ago. Please take a look at https://lkml.org/lkml/2019/7/1/25 and talk to Manish to resolve this. Thanks, Michal