On 09/21/2012 07:36 AM, Borislav Petkov wrote:
> Ok, I think this is still the old code you're looking at so it would be
> cool if you could test with my patchset I sent you last week.
>
> Because with it, it all looks fine on my K8 here:
>
> It has 2 2048MB single-ranked DIMMs on each node and edac output looks
> like this:
>
> [   52.920302] EDAC DEBUG: amd64_debug_display_dimm_sizes: F2x080 (DRAM Bank Address Mapping): 0x00000060
> [   52.920302] EDAC MC: DCT0 chip selects:
> [   52.920304] EDAC amd64: MC: 0:     0MB 1:     0MB
> [   52.920305] EDAC amd64: MC: 2:  2048MB 3:  2048MB
> [   52.920306] EDAC amd64: MC: 4:     0MB 5:     0MB
> [   52.920308] EDAC amd64: MC: 6:     0MB 7:     0MB
>
> ...
>
> [   52.920344] EDAC DEBUG: init_csrows: node 1, NBCFG=0x0ad00044[ChipKillEccCap: 1|DramEccEn: 1]
> [   52.920345] EDAC DEBUG: init_csrows: MC node: 1, csrow: 2
> [   52.920346] EDAC DEBUG: amd64_csrow_nr_pages: csrow: 2, channel: 0, DBAM idx: 6
> [   52.920347] EDAC DEBUG: amd64_csrow_nr_pages: nr_pages/channel: 524288
> [   52.920348] EDAC amd64: CS2: Registered DDR2 RAM
> [   52.920350] EDAC DEBUG: init_csrows: Total csrow2 pages: 524288
> [   52.920351] EDAC DEBUG: init_csrows: MC node: 1, csrow: 3
> [   52.920352] EDAC DEBUG: amd64_csrow_nr_pages: csrow: 3, channel: 0, DBAM idx: 6
> [   52.920353] EDAC DEBUG: amd64_csrow_nr_pages: nr_pages/channel: 524288
> [   52.920354] EDAC amd64: CS3: Registered DDR2 RAM
> [   52.920355] EDAC DEBUG: init_csrows: Total csrow3 pages: 524288
>
> $ cat /sys/devices/system/edac/mc/mc0/csrow2/size_mb
> 2048
> $ cat /sys/devices/system/edac/mc/mc0/csrow3/size_mb
> 2048
>
> So what am I missing?
>
> Thanks.

I'm running with your edac-queue branch with the last commit being:
  9d67117feece8852570cc8ee25b68c41f8def323

You can verify this with my dmesg (also attached) showing the new dbg 
messages added:

<patch>
+       edac_dbg(0, "csrow: %d, channel: %d, DBAM idx: %d\n",
+                   csrow_nr, dct,  cs_mode);
+       edac_dbg(0, "nr_pages/channel: %u\n", nr_pages);
</patch>

<dmesg>
[   25.838822] EDAC DEBUG: amd64_csrow_nr_pages: csrow: 3, channel: 0, 
DBAM idx: 2
[   25.838823] EDAC DEBUG: amd64_csrow_nr_pages: nr_pages/channel: 262144
</dmesg>

Please let me know if this is the wrong version and I can rerun with the 
correct one.

Here's what I see in sysfs:
root@x.x.x.x:/sys/devices/system/edac/mc/mc0# grep . csrow*/size_mb
csrow0/size_mb:2048
csrow1/size_mb:2048
csrow2/size_mb:2048
csrow3/size_mb:2048

Here's what free reports:
root@x.x.x.x:/sys/devices/system/edac/mc/mc0# free
              total       used       free     shared    buffers     cached
Mem:       4057308     159300    3898008          0       3972      79048
-/+ buffers/cache:      76280    3981028
Swap:      4192960          0    4192960

IIRC the issue I was pointing out in my last mail is the code detected 2 
channels on my system. Which appeared to lead to double counting in the 
sysfs code. The channel detection code in
k8_early_channel_count() returns 2 when WIDTH_128 is set.

If you're seeing it behave correctly on your system I wonder if the 
WIDTH_128 bit is true for your machine?

Josh