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Fri, 18 Jan 2019 09:13:30 +0000 (GMT) Subject: Re: [PATCH 2/8] drm/meson: add HDMI div40 TMDS mode To: Neil Armstrong , Laurent.pinchart@ideasonboard.com Cc: dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org From: Andrzej Hajda Message-ID: <5103b2e8-2f73-da18-a043-fa45d6e2c139@samsung.com> Date: Fri, 18 Jan 2019 10:13:28 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: <20190115123315.11069-3-narmstrong@baylibre.com> Content-Transfer-Encoding: 8bit Content-Language: en-US X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprHKsWRmVeSWpSXmKPExsWy7djP87q7ZzjGGOzs4bC48vU9m0XnxCXs Fgtmc1tc3jWHzeJQX7QDq8f7G63sHrM7ZrJ63O8+zuSxeUm9x+dNcgGsUVw2Kak5mWWpRfp2 CVwZqy5+Yi84LF4x78FZpgbGncJdjJwcEgImEptXPWbvYuTiEBJYwSix9eMlRgjnC6PErf/b WSGcz4wSh3fPZ4Rpeb/3JlTVckaJLRfaoKreMkos/trIBlIlLGAj8XDND3YQW0QgUOJ47zaw bmaBNIlbMw6xgthsApoSfzffBKvnFbCTmPnmFFicRUBVYvasn2D1ogIREh33V0PVCEqcnPmE BcTmFLCVmD9vMzvETHmJ5q2zmSFscYlbT+YzgRwkITCPXWLC8tXMEGe7SNzacp8JwhaWeHV8 CzuELSPxf+d8qHi9RNPMK8wQzR2MEicWL2eDSFhLHD5+Eeg6DqANmhLrd+lDhB0lNrwGOZQD yOaTuPFWEOIGPolJ26YzQ4R5JTrahCCqFSXun90KdY24xNILX9kmMCrNQvLZLCTfzELyzSyE vQsYWVYxiqeWFuempxYb5aWW6xUn5haX5qXrJefnbmIEpprT/45/2cG460/SIUYBDkYlHt4J WxxihFgTy4orcw8xSnAwK4nwGkx1jBHiTUmsrEotyo8vKs1JLT7EKM3BoiTOW83wIFpIID2x JDU7NbUgtQgmy8TBKdXA6Hfp5rdFCdoqBYcXVMVzXAraVzm/eOaU8/+sdyc51T4U6lYS2PJh 8efsTeqMhz5nV54PPh8avO/aZ/l1G19F//78wqVm9v0tJ3Rq1DZVTzj1cNvJhh0zmVfw3ff/ naE1YeWHNWZ6zHbaKfXVx9dz5yb0Rbsdk0+zurNZfcGCsEvMQb63ufNmBSmxFGckGmoxFxUn AgAZABElMQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrIIsWRmVeSWpSXmKPExsVy+t/xu7q7ZjjGGBw4KmJx5et7NovOiUvY LRbM5ra4vGsOm8WhvmgHVo/3N1rZPWZ3zGT1uN99nMlj85J6j8+b5AJYo/RsivJLS1IVMvKL S2yVog0tjPQMLS30jEws9QyNzWOtjEyV9O1sUlJzMstSi/TtEvQyVl38xF5wWLxi3oOzTA2M O4W7GDk5JARMJN7vvcnYxcjFISSwlFHizYJfjBAJcYnd898yQ9jCEn+udbFBFL1mlLgwdRNY QljARuLhmh/sILaIQKDEot4FYHFmgTSJP09BmkEaDjNKnL47kwkkwSagKfF38002EJtXwE5i 5ptTrCA2i4CqxOxZP8E2iwpESJx9uY4RokZQ4uTMJywgNqeArcT8eZvZIRaoS/yZdwlqmbxE 89bZULa4xK0n85kmMArNQtI+C0nLLCQts5C0LGBkWcUoklpanJueW2yoV5yYW1yal66XnJ+7 iREYXduO/dy8g/HSxuBDjAIcjEo8vC+2OcQIsSaWFVfmHmKU4GBWEuE1mOoYI8SbklhZlVqU H19UmpNafIjRFOi5icxSosn5wMjPK4k3NDU0t7A0NDc2NzazUBLnPW9QGSUkkJ5YkpqdmlqQ WgTTx8TBKdXAWPX0WsuDlPQn34IVf5w2qNh3yn0pm7nn440rNnDPCQic//Pd/ezr3uxpRyea q36Ofb5l98zQU0lHFvEFzVQ9U/3swg/+/0v+/ImQCbG4nl77Tr1QfMnZRDbJ2eLuXlufG7Xz x/JzLGhpMuGNUL8+kzfs8hnN42YvvC+YePu8vmd9cKbSJOktpkosxRmJhlrMRcWJAOfyCnnE AgAA X-CMS-MailID: 20190118091330eucas1p2478410cf9299c2a3073b48d638a71123 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20190115123329epcas2p238b0b8a9f449f96991e02b34c54741ca X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190115123329epcas2p238b0b8a9f449f96991e02b34c54741ca References: <20190115123315.11069-1-narmstrong@baylibre.com> <20190115123315.11069-3-narmstrong@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 15.01.2019 13:33, Neil Armstrong wrote: > Add support for TMDS Clock > 3.4GHz for HDMI2.0 display modes. > > Signed-off-by: Neil Armstrong > --- > drivers/gpu/drm/meson/meson_dw_hdmi.c | 23 +++++++++++++++++++---- > 1 file changed, 19 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c > index 807111ebfdd9..3d8decb77019 100644 > --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c > +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c > @@ -365,7 +365,8 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, > unsigned int wr_clk = > readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING)); > > - DRM_DEBUG_DRIVER("%d:\"%s\"\n", mode->base.id, mode->name); > + DRM_DEBUG_DRIVER("%d:\"%s\" div%d\n", mode->base.id, mode->name, > + mode->clock > 340000 ? 40 : 10); > > /* Enable clocks */ > regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); > @@ -385,9 +386,17 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, > /* Enable normal output to PHY */ > dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12)); > > - /* TMDS pattern setup (TOFIX pattern for 4k2k scrambling) */ > - dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0x001f001f); > - dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, 0x001f001f); > + /* TMDS pattern setup (TOFIX Handle the YUV420 case) */ > + if (mode->clock > 340000) { > + dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0); > + dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, > + 0x03ff03ff); > + } else { > + dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, > + 0x001f001f); > + dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, > + 0x001f001f); > + }     val = mode->clock > 340000 ? 0x03ff03ff : 0x001f001f;     dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, val);     dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, val); The best would be to replace these magic values with descriptive macros. Regards Andrzej > > /* Load TMDS pattern */ > dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1); > @@ -413,6 +422,8 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, > /* Disable clock, fifo, fifo_wr */ > regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0); > > + dw_hdmi_set_high_tmds_clock_ratio(hdmi); > + > msleep(100); > > /* Reset PHY 3 times in a row */ > @@ -562,6 +573,10 @@ dw_hdmi_mode_valid(struct drm_connector *connector, > mode->vdisplay, mode->vsync_start, > mode->vsync_end, mode->vtotal, mode->type, mode->flags); > > + /* If sink max TMDS clock, we reject the mode */ > + if (mode->clock > connector->display_info.max_tmds_clock) > + return MODE_BAD; > + > /* Check against non-VIC supported modes */ > if (!vic) { > status = meson_venc_hdmi_supported_mode(mode);