From: Paolo Bonzini <pbonzini@redhat.com>
To: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
x86@kernel.org
Cc: joro@8bytes.org, tglx@linutronix.de, mingo@redhat.com,
bp@alien8.de, peterz@infradead.org, hpa@zytor.com,
thomas.lendacky@amd.com, jon.grimm@amd.com
Subject: Re: [PATCH 2/2] KVM: SVM: Extend host physical APIC ID field to support more than 8-bit
Date: Wed, 17 Nov 2021 14:06:59 +0100 [thread overview]
Message-ID: <5148de60-4a9d-67ef-ca64-5c6461034c0c@redhat.com> (raw)
In-Reply-To: <20211110101805.16343-3-suravee.suthikulpanit@amd.com>
On 11/10/21 11:18, Suravee Suthikulpanit wrote:
> + if (level_type != 2 || !x2apic_mode) {
> + avic_host_physical_id_mask = 0xffULL;
> + goto out;
> + }
> +
> + core_mask_width = eax & 0xF;
> +
> + max_phys_mask_width = get_count_order(apic_get_max_phys_apicid());
> +
> + /*
> + * Sanity check to ensure core_mask_width for a processor does not
> + * exceed the calculated mask.
> + */
> + if (WARN_ON(core_mask_width > max_phys_mask_width))
> + return -EINVAL;
Can it just use apic_get_max_phys_apicid() in x2apic mode, and 0xff in
!x2apic mode? I'm not sure why you need to check CPUID[0xb,0x1].
Paolo
next prev parent reply other threads:[~2021-11-17 13:07 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-10 10:18 [PATCH 0/2] svm: avic: Allow AVIC support on system w/ physical APIC ID > 255 Suravee Suthikulpanit
2021-11-10 10:18 ` [PATCH 1/2] x86/apic: Add helper function to get maximum physical APIC ID Suravee Suthikulpanit
2021-11-10 10:18 ` [PATCH 2/2] KVM: SVM: Extend host physical APIC ID field to support more than 8-bit Suravee Suthikulpanit
2021-11-10 19:48 ` Sean Christopherson
2021-11-16 10:29 ` Suthikulpanit, Suravee
2021-11-17 13:06 ` Paolo Bonzini [this message]
2021-12-01 15:13 ` Suthikulpanit, Suravee
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