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From: "Steven J. Hill" <sjhill@realitydiluted.com>
To: Huacai Chen <chenhc@lemote.com>
Cc: Ralf Baechle <ralf@linux-mips.org>,
	linux-mips@linux-mips.org, linux-kernel@vger.kernel.org,
	Fuxin Zhang <zhangfx@lemote.com>,
	Zhangjin Wu <wuzhangjin@gmail.com>,
	Hongliang Tao <taohl@lemote.com>, Hua Yan <yanh@lemote.com>
Subject: Re: [PATCH V9 03/13] MIPS: Loongson: Introduce and use cpu_has_coherent_cache feature
Date: Thu, 11 Apr 2013 12:05:42 -0500	[thread overview]
Message-ID: <5166ED66.7020307@realitydiluted.com> (raw)
In-Reply-To: <1359527106-22879-4-git-send-email-chenhc@lemote.com>

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On 01/30/2013 12:24 AM, Huacai Chen wrote:
> Loongson-3 maintains cache coherency by hardware. So we introduce a cpu 
> feature named cpu_has_coherent_cache and use it to modify MIPS's cache 
> flushing functions.
> 
> Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao
> <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> --- 
> arch/mips/include/asm/cacheflush.h                 |    6 +++++ 
> arch/mips/include/asm/cpu-features.h               |    3 ++ 
> .../asm/mach-loongson/cpu-feature-overrides.h      |    6 +++++ 
> arch/mips/mm/c-r4k.c                               |   21
> ++++++++++++++++++- 4 files changed, 34 insertions(+), 2 deletions(-)
> 
Hello.

This patch masks the problem that you are not properly probing your L1 caches
to start with. For some reason in 'probe_pcache()' you reach the default case
where the primary data cache is marked as having aliases. If your CPU truly is
HW coherent with no aliases, then MIPS_CACHE_ALIASES should never get set.
Fixing this would eliminate the 'arch/mips/include/asm/cacheflush.h' and
'arch/mips/mm/c-r4k.c' changes completely. There is no need to add more CPU
feature bits for this single platform, thus changes to 'cpu-features.h' and
'cpu-features-overrides.h' will not be accepted.

Also, please do not copy the <linux-kernel@vger.kernel.org> mailing list
unless your patch touches files outside of 'arch/mips' in order to cut down
traffic on an already busy list. Thanks.

Steve
- -----
<sjhill@mips.com>
<Steven.Hill@imgtec.com>
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  reply	other threads:[~2013-04-11 17:24 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-01-30  6:24 [PATCH V9 00/13] MIPS: Add Loongson-3 based machines support Huacai Chen
2013-01-30  6:24 ` [PATCH V9 01/13] MIPS: Loongson: Add basic Loongson-3 definition Huacai Chen
2013-01-30  6:24 ` [PATCH V9 02/13] MIPS: Loongson: Add basic Loongson-3 CPU support Huacai Chen
2013-01-30  6:24 ` [PATCH V9 03/13] MIPS: Loongson: Introduce and use cpu_has_coherent_cache feature Huacai Chen
2013-04-11 17:05   ` Steven J. Hill [this message]
     [not found]     ` <CAAhV-H6s47NUHzbEX5UKYtkei7=s08PPXCMw39_fP_SV7Hv5Vg@mail.gmail.com>
2013-06-23  2:10       ` Huacai Chen
2013-06-24 22:39         ` Steven J. Hill
2013-06-25  5:14           ` chenhc
2013-01-30  6:24 ` [PATCH V9 04/13] MIPS: Loongson 3: Add Lemote-3A machtypes definition Huacai Chen
2013-01-30  6:24 ` [PATCH V9 05/13] MIPS: Loongson: Add UEFI-like firmware interface support Huacai Chen
2013-01-30  6:24 ` [PATCH V9 06/13] MIPS: Loongson 3: Add HT-linked PCI support Huacai Chen
2013-01-30  6:25 ` [PATCH V9 07/13] MIPS: Loongson 3: Add IRQ init and dispatch support Huacai Chen
2013-01-30  6:25 ` [PATCH V9 08/13] MIPS: Loongson 3: Add serial port support Huacai Chen
2013-01-30  6:25 ` [PATCH V9 09/13] MIPS: Loongson: Add swiotlb to support big memory (>4GB) Huacai Chen
2013-01-30  6:25 ` [PATCH V9 10/13] MIPS: Loongson: Add Loongson-3 Kconfig options Huacai Chen
2013-01-30  6:25 ` [PATCH V9 11/13] MIPS: Loongson 3: Add Loongson-3 SMP support Huacai Chen
2013-01-30  6:25 ` [PATCH V9 12/13] MIPS: Loongson 3: Add CPU hotplug support Huacai Chen
2013-01-30  6:25 ` [PATCH V9 13/13] MIPS: Loongson: Add a Loongson-3 default config file Huacai Chen

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