From: Mukesh Ojha <quic_mojha@quicinc.com>
To: Poovendhan Selvaraj <quic_poovendh@quicinc.com>,
<agross@kernel.org>, <andersson@kernel.org>,
<konrad.dybcio@linaro.org>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <lee@kernel.org>,
<catalin.marinas@arm.com>, <will@kernel.org>,
<shawnguo@kernel.org>, <arnd@arndb.de>,
<marcel.ziswiler@toradex.com>, <robimarko@gmail.com>,
<dmitry.baryshkov@linaro.org>, <nfraprado@collabora.com>,
<broonie@kernel.org>, <quic_gurus@quicinc.com>,
<linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Cc: <quic_srichara@quicinc.com>, <quic_gokulsri@quicinc.com>,
<quic_sjaganat@quicinc.com>, <quic_kathirav@quicinc.com>,
<quic_arajkuma@quicinc.com>, <quic_anusha@quicinc.com>,
<quic_devipriy@quicinc.com>
Subject: Re: [PATCH V5 5/5] firmware: scm: Modify only the DLOAD bit in TCSR register for download mode
Date: Thu, 16 Feb 2023 19:30:53 +0530 [thread overview]
Message-ID: <51bd93be-f8d3-a33c-18ad-ba4a331f2bcf@quicinc.com> (raw)
In-Reply-To: <20230216120012.28357-6-quic_poovendh@quicinc.com>
On 2/16/2023 5:30 PM, Poovendhan Selvaraj wrote:
> CrashDump collection is based on the DLOAD bit of TCSR register.
> To retain other bits, we read the register and modify only the DLOAD bit as
> the other bits have their own significance.
>
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Co-developed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> Signed-off-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
> ---
> Changes in V5:
> - checking the return value in qcom_scm_set_download_mode function as
> suggested by Srinivas Kandagatla
>
> Changes in V4:
> - retain the orginal value of tcsr register when download mode
> is not set
>
> drivers/firmware/qcom_scm.c | 21 ++++++++++++++++-----
> 1 file changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
> index 468d4d5ab550..d88c5f14bd54 100644
> --- a/drivers/firmware/qcom_scm.c
> +++ b/drivers/firmware/qcom_scm.c
> @@ -407,7 +407,7 @@ int qcom_scm_set_remote_state(u32 state, u32 id)
> }
> EXPORT_SYMBOL(qcom_scm_set_remote_state);
>
> -static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
> +static int __qcom_scm_set_dload_mode(struct device *dev, u32 val, bool enable)
> {
> struct qcom_scm_desc desc = {
> .svc = QCOM_SCM_SVC_BOOT,
> @@ -417,7 +417,8 @@ static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
> .owner = ARM_SMCCC_OWNER_SIP,
> };
>
> - desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
> + desc.args[1] = enable ? val | QCOM_SCM_BOOT_SET_DLOAD_MODE :
> + val & ~(QCOM_SCM_BOOT_SET_DLOAD_MODE);
>
> return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
> }
> @@ -426,15 +427,25 @@ static void qcom_scm_set_download_mode(bool enable)
> {
> bool avail;
> int ret = 0;
> + u32 dload_addr_val;
>
> avail = __qcom_scm_is_call_available(__scm->dev,
> QCOM_SCM_SVC_BOOT,
> QCOM_SCM_BOOT_SET_DLOAD_MODE);
> + ret = qcom_scm_io_readl(__scm->dload_mode_addr, &dload_addr_val);
> +
> + if (ret) {
> + dev_err(__scm->dev,
> + "failed to read dload mode address value: %d\n", ret);
> + return;
> + }
> +
> if (avail) {
> - ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
> + ret = __qcom_scm_set_dload_mode(__scm->dev, dload_addr_val, enable);
Did you test this on a target where it comes under this if statement?
does it really need to know dload_mode_addr for this target ?
-Mukesh
> } else if (__scm->dload_mode_addr) {
> - ret = qcom_scm_io_writel(__scm->dload_mode_addr,
> - enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
> + ret = qcom_scm_io_writel(__scm->dload_mode_addr, enable ?
> + dload_addr_val | QCOM_SCM_BOOT_SET_DLOAD_MODE :
> + dload_addr_val & ~(QCOM_SCM_BOOT_SET_DLOAD_MODE));
> } else {
> dev_err(__scm->dev,
> "No available mechanism for setting download mode\n");
next prev parent reply other threads:[~2023-02-16 14:01 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-16 12:00 [PATCH V5 0/5] Enable crashdump collection support for IPQ9574 Poovendhan Selvaraj
2023-02-16 12:00 ` [PATCH V5 1/5] dt-bindings: scm: Add compatible " Poovendhan Selvaraj
2023-02-16 12:00 ` [PATCH V5 2/5] dt-bindings: mfd: Add the tcsr " Poovendhan Selvaraj
2023-02-16 12:00 ` [PATCH V5 3/5] arm64: dts: qcom: ipq9574: Enable the download mode support Poovendhan Selvaraj
2023-02-16 12:00 ` [PATCH V5 4/5] arm64: dts: qcom: ipq9574: Add SMEM support Poovendhan Selvaraj
2023-02-16 12:00 ` [PATCH V5 5/5] firmware: scm: Modify only the DLOAD bit in TCSR register for download mode Poovendhan Selvaraj
2023-02-16 14:00 ` Mukesh Ojha [this message]
2023-02-17 19:49 ` Mukesh Ojha
2023-02-20 10:30 ` POOVENDHAN SELVARAJ
2023-02-22 6:52 ` Sricharan Ramabadhran
2023-02-22 7:22 ` Mukesh Ojha
2023-02-22 7:49 ` Sricharan Ramabadhran
2023-03-15 23:35 ` (subset) [PATCH V5 0/5] Enable crashdump collection support for IPQ9574 Bjorn Andersson
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