From: Shanker R Donthineni <sdonthineni@nvidia.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: Alex Williamson <alex.williamson@redhat.com>,
Bjorn Helgaas <bhelgaas@google.com>, <linux-pci@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, Sinan Kaya <okaya@kernel.org>,
Vikram Sethi <vsethi@nvidia.com>,
Amey Narkhede <ameynarkhede03@gmail.com>
Subject: Re: [PATCH v4 2/2] PCI: Enable NO_BUS_RESET quirk for Nvidia GPUs
Date: Fri, 30 Apr 2021 17:11:23 -0500 [thread overview]
Message-ID: <52c89d4e-6b26-6c56-d71e-508a715394ab@nvidia.com> (raw)
In-Reply-To: <20210430170151.GA660969@bjorn-Precision-5520>
Thanks Bjorn for reviewing patch.
On 4/30/21 12:01 PM, Bjorn Helgaas wrote:
> External email: Use caution opening links or attachments
>
>
> On Wed, Apr 28, 2021 at 07:49:07PM -0500, Shanker Donthineni wrote:
>> On select platforms, some Nvidia GPU devices do not work with SBR.
>> Triggering SBR would leave the device inoperable for the current
>> system boot. It requires a system hard-reboot to get the GPU device
>> back to normal operating condition post-SBR. For the affected
>> devices, enable NO_BUS_RESET quirk to fix the issue.
> Since 1/2 adds _RST support, should I infer that _RST works on these
> Nvidia GPUs even though SBR does not? If so, how does _RST do the
> reset?
Yes, _RST method works but not SBR. The _RST method in DSDT-AML uses
platform-specific initialization steps outside of the GPU BARs for resetting
the GPU device.
> Do you have a root cause for why SBR doesn't work?
It is a hardware implementation specific issue. GPU end-point device
is inoperative after receiving SBR from the RP/SwitchPort. This quirk is
to prevent SBR.
> I'm not super
> confident that we perform resets correctly in general, and if the
> problem is an issue in Linux, it'd be nice to fix that.
We have not seen any issue with Linux SBR implementation.
>
>> This issue will be fixed in the next generation of hardware.
>>
>> Signed-off-by: Shanker Donthineni <sdonthineni@nvidia.com>
>> ---
>> Changes since v1:
>> - Split patch into 2, code for handling _RST and SBR specific quirk
>> - The RST based reset is called as a first-class mechanism in the reset code path
>>
>> drivers/pci/quirks.c | 12 ++++++++++++
>> 1 file changed, 12 insertions(+)
>>
>> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
>> index 8f47d139c381..e1216a8165df 100644
>> --- a/drivers/pci/quirks.c
>> +++ b/drivers/pci/quirks.c
>> @@ -3910,6 +3910,18 @@ static int delay_250ms_after_flr(struct pci_dev *dev, int probe)
>> return 0;
>> }
>>
>> +/*
>> + * Some Nvidia GPU devices do not work with bus reset, SBR needs to be
>> + * prevented for those affected devices.
>> + */
>> +static void quirk_nvidia_no_bus_reset(struct pci_dev *dev)
>> +{
>> + if ((dev->device & 0xffc0) == 0x2340)
>> + dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
>> +}
>> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
>> + quirk_nvidia_no_bus_reset);
> Can you move this next to the existing quirk_no_bus_reset(), and maybe
> even just call quirk_no_bus_reset(), e.g.,
>
> if ((dev->device & 0xffc0) == 0x2340)
> quirk_no_bus_reset(dev);
>
> It doesn't look connected to this spot.
>
Thanks, I will move next to the existing NO_BUS_RESET quirks.
>> static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
>> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
>> reset_intel_82599_sfp_virtfn },
>> --
>> 2.17.1
>>
next prev parent reply other threads:[~2021-04-30 22:11 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-29 0:49 [PATCH v4 1/2] PCI: Add support for a function level reset based on _RST method Shanker Donthineni
2021-04-29 0:49 ` [PATCH v4 2/2] PCI: Enable NO_BUS_RESET quirk for Nvidia GPUs Shanker Donthineni
2021-04-30 17:01 ` Bjorn Helgaas
2021-04-30 22:11 ` Shanker R Donthineni [this message]
2021-05-03 22:42 ` Bjorn Helgaas
2021-05-04 2:07 ` Shanker R Donthineni
2021-05-05 2:12 ` Bjorn Helgaas
2021-05-05 3:51 ` Shanker R Donthineni
2021-05-05 3:56 ` Oliver O'Halloran
2021-05-05 17:40 ` Amey Narkhede
2021-05-05 19:13 ` Alex Williamson
2021-05-05 20:04 ` Shanker R Donthineni
2021-05-05 20:40 ` Bjorn Helgaas
2021-05-05 12:15 ` Pali Rohár
2021-05-05 15:35 ` Shanker R Donthineni
2021-04-30 18:39 ` [PATCH v4 1/2] PCI: Add support for a function level reset based on _RST method Alex Williamson
2021-04-30 19:05 ` Shanker R Donthineni
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=52c89d4e-6b26-6c56-d71e-508a715394ab@nvidia.com \
--to=sdonthineni@nvidia.com \
--cc=alex.williamson@redhat.com \
--cc=ameynarkhede03@gmail.com \
--cc=bhelgaas@google.com \
--cc=helgaas@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=okaya@kernel.org \
--cc=vsethi@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).