From: gengdongjiu <gengdongjiu@huawei.com>
To: James Morse <james.morse@arm.com>
Cc: <christoffer.dall@linaro.org>, <marc.zyngier@arm.com>,
<linux@armlinux.org.uk>, <catalin.marinas@arm.com>,
<rjw@rjwysocki.net>, <bp@alien8.de>, <robert.moore@intel.com>,
<lv.zheng@intel.com>, <corbet@lwn.net>, <will.deacon@arm.com>,
<linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<kvmarm@lists.cs.columbia.edu>, <linux-acpi@vger.kernel.org>,
<devel@acpica.org>, <huangshaoyu@huawei.com>
Subject: Re: [PATCH v9 3/7] acpi: apei: Add SEI notification type support for ARMv8
Date: Tue, 23 Jan 2018 18:07:52 +0800 [thread overview]
Message-ID: <53566b7c-d686-66be-ee84-a6a6257b526a@huawei.com> (raw)
In-Reply-To: <168c3f61-0d11-13a4-c383-1f6a97d0ef37@huawei.com>
sorry fix a typo.
On 2018/1/23 17:23, gengdongjiu wrote:
>> There are problems with doing this:
>>
>> Oct. 18, 2017, 10:26 a.m. James Morse wrote:
>> | How do SEA and SEI interact?
>> |
>> | As far as I can see they can both interrupt each other, which isn't something
>> | the single in_nmi() path in APEI can handle. I thinks we should fix this
>> | first.
>>
>> [..]
>>
>> | SEA gets away with a lot of things because its synchronous. SEI isn't. Xie
>> | XiuQi pointed to the memory_failure_queue() code. We can use this directly
>> | from SEA, but not SEI. (what happens if an SError arrives while we are
>> | queueing memory_failure work from an IRQ).
>> |
>> | The one that scares me is the trace-point reporting stuff. What happens if an
>> | SError arrives while we are enabling a trace point? (these are static-keys
>> | right?)
>> |
>> | I don't think we can just plumb SEI in like this and be done with it.
>> | (I'm looking at teasing out the estatus cache code from being x86:NMI only.
>> | This way we solve the same 'cant do this from NMI context' with the same
>> | code'.)
>>
>>
>> I will post what I've got for this estatus-cache thing as an RFC, its not ready
>> to be considered yet.
Yes, I know you are dong that. Your serial's patch will consider all above things, right?
If your patch can be consider that, this patch can based on your patchset. thanks.
>
>>
next prev parent reply other threads:[~2018-01-23 10:09 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-06 16:02 [PATCH v9 0/7] Handle guest RAS Error in KVM and kernel Dongjiu Geng
2018-01-06 16:02 ` [PATCH v9 1/7] arm64: cpufeature: Detect CPU RAS Extentions Dongjiu Geng
2018-01-06 16:02 ` [PATCH v9 2/7] KVM: arm64: Save ESR_EL2 on guest SError Dongjiu Geng
2018-01-06 16:02 ` [PATCH v9 3/7] acpi: apei: Add SEI notification type support for ARMv8 Dongjiu Geng
2018-01-22 19:39 ` James Morse
2018-01-23 9:23 ` gengdongjiu
2018-01-23 10:07 ` gengdongjiu [this message]
2018-01-30 19:39 ` James Morse
2018-01-06 16:02 ` [PATCH v9 4/7] KVM: arm64: Trap RAS error registers and set HCR_EL2's TERR & TEA Dongjiu Geng
2018-01-06 16:02 ` [PATCH v9 5/7] arm64: kvm: Introduce KVM_ARM_SET_SERROR_ESR ioctl Dongjiu Geng
2018-01-23 19:06 ` James Morse
2018-01-06 16:02 ` [PATCH v9 6/7] arm64: kvm: Set Virtual SError Exception Syndrome for guest Dongjiu Geng
2018-01-23 19:07 ` James Morse
2018-01-25 8:21 ` gengdongjiu
2018-01-06 16:02 ` [PATCH v9 7/7] arm64: kvm: handle guest SError Interrupt by categorization Dongjiu Geng
2018-02-05 11:24 [PATCH v9 3/7] acpi: apei: Add SEI notification type support for ARMv8 gengdongjiu
2018-02-15 17:55 ` James Morse
2018-04-12 5:00 ` gengdongjiu
2018-04-12 16:14 ` James Morse
2018-04-13 13:50 ` gengdongjiu
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