From: Robin Murphy <robin.murphy@arm.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: Javier Martinez Canillas <javierm@redhat.com>,
linux-kernel@vger.kernel.org,
Peter Robinson <pbrobinson@gmail.com>,
Shawn Lin <shawn.lin@rock-chips.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Heiko Stuebner <heiko@sntech.de>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh@kernel.org>,
linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
linux-rockchip@lists.infradead.org
Subject: Re: [PATCH v2] PCI: rockchip: Avoid accessing PCIe registers with clocks gated
Date: Fri, 25 Jun 2021 00:51:16 +0100 [thread overview]
Message-ID: <5356a01c-5aab-fbff-b0a9-157b961c66ee@arm.com> (raw)
In-Reply-To: <20210624232841.GA3579021@bjorn-Precision-5520>
On 2021-06-25 00:28, Bjorn Helgaas wrote:
> On Fri, Jun 25, 2021 at 12:18:48AM +0100, Robin Murphy wrote:
>> On 2021-06-24 22:57, Bjorn Helgaas wrote:
>>> On Tue, Jun 08, 2021 at 10:04:09AM +0200, Javier Martinez Canillas wrote:
>>>> IRQ handlers that are registered for shared interrupts can be called at
>>>> any time after have been registered using the request_irq() function.
>>>>
>>>> It's up to drivers to ensure that's always safe for these to be called.
>>>>
>>>> Both the "pcie-sys" and "pcie-client" interrupts are shared, but since
>>>> their handlers are registered very early in the probe function, an error
>>>> later can lead to these handlers being executed before all the required
>>>> resources have been properly setup.
>>>>
>>>> For example, the rockchip_pcie_read() function used by these IRQ handlers
>>>> expects that some PCIe clocks will already be enabled, otherwise trying
>>>> to access the PCIe registers causes the read to hang and never return.
>>>
>>> The read *never* completes? That might be a bit problematic because
>>> it implies that we may not be able to recover from PCIe errors. Most
>>> controllers will timeout eventually, log an error, and either
>>> fabricate some data (typically ~0) to complete the CPU's read or cause
>>> some kind of abort or machine check.
>>>
>>> Just asking in case there's some controller configuration that should
>>> be tweaked.
>>
>> If I'm following correctly, that'll be a read transaction to the native side
>> of the controller itself; it can't complete that read, or do anything else
>> either, because it's clock-gated, and thus completely oblivious (it might be
>> that if another CPU was able to enable the clocks then everything would
>> carry on as normal, or it might end up totally deadlocking the SoC
>> interconnect). I think it's safe to assume that in that state nothing of
>> importance would be happening on the PCIe side, and even if it was we'd
>> never get to know about it.
>
> Oh, right, that makes sense. I was thinking about the PCIe side, but
> if the controller itself isn't working, of course we wouldn't get that
> far.
>
> I would expect that the CPU itself would have some kind of timeout for
> the read, but that's far outside of the PCI world.
Nah, in AMBA I'm not sure if it's even legal to abandon a transaction
without waiting for the handshake to complete. If you're lucky the
interconnect might have a clock/power domain bridge which can reply with
an error when it knows its other side isn't running, otherwise the
initiator will just happily sit there waiting for a response to come
back "in a timely manner" :)
Robin.
next prev parent reply other threads:[~2021-06-24 23:51 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-08 8:04 [PATCH v2] PCI: rockchip: Avoid accessing PCIe registers with clocks gated Javier Martinez Canillas
2021-06-12 22:02 ` Peter Robinson
2021-06-22 10:31 ` Lorenzo Pieralisi
2021-06-24 21:57 ` Bjorn Helgaas
2021-06-24 23:18 ` Robin Murphy
2021-06-24 23:28 ` Bjorn Helgaas
2021-06-24 23:51 ` Robin Murphy [this message]
2021-06-24 22:40 ` Bjorn Helgaas
2021-06-25 7:09 ` Javier Martinez Canillas
2021-06-25 14:32 ` Bjorn Helgaas
2021-06-25 18:34 ` Javier Martinez Canillas
2021-06-29 0:38 ` Bjorn Helgaas
2021-06-29 6:17 ` Javier Martinez Canillas
2021-06-29 10:52 ` Robin Murphy
2021-06-29 23:14 ` Bjorn Helgaas
2021-06-30 9:44 ` Robin Murphy
2021-06-30 18:49 ` Bjorn Helgaas
2021-06-30 18:59 ` Bjorn Helgaas
2021-06-30 19:59 ` Javier Martinez Canillas
2021-06-30 20:30 ` Bjorn Helgaas
2021-06-30 20:46 ` Peter Robinson
2021-06-30 22:09 ` Javier Martinez Canillas
2021-07-01 13:59 ` Bjorn Helgaas
2021-07-01 14:59 ` Javier Martinez Canillas
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