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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jami Kettunen Cc: Alex Elder , linux-kernel@vger.kernel.org, netdev@vger.kernel.org References: <20221024210336.4014983-1-caleb.connolly@linaro.org> <20221024210336.4014983-2-caleb.connolly@linaro.org> From: Alex Elder In-Reply-To: <20221024210336.4014983-2-caleb.connolly@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/24/22 4:03 PM, Caleb Connolly wrote: > The resource group limits for IPA v3.1 mistakenly used 6 bit wide mask > values, when the hardware actually uses 8. Out of range values were > silently ignored before, so the IPA worked as expected. However the > new generalised register definitions introduce stricter checking here, > they now cause some splats and result in the value 0 being written > instead. Fix the limit bitmask widths so that the correct values can be > written. > > Fixes: 1c418c4a929c ("net: ipa: define resource group/type IPA register fields") > Signed-off-by: Caleb Connolly Looks good to me, thanks for fixing this. Note: this is for net/master, to be back-ported to v6.0.y. Reviewed-by: Alex Elder > --- > drivers/net/ipa/reg/ipa_reg-v3.1.c | 96 ++++++++++-------------------- > 1 file changed, 32 insertions(+), 64 deletions(-) > > diff --git a/drivers/net/ipa/reg/ipa_reg-v3.1.c b/drivers/net/ipa/reg/ipa_reg-v3.1.c > index 116b27717e3d..0d002c3c38a2 100644 > --- a/drivers/net/ipa/reg/ipa_reg-v3.1.c > +++ b/drivers/net/ipa/reg/ipa_reg-v3.1.c > @@ -127,112 +127,80 @@ static const u32 ipa_reg_counter_cfg_fmask[] = { > IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); > > static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { > - [X_MIN_LIM] = GENMASK(5, 0), > - /* Bits 6-7 reserved */ > - [X_MAX_LIM] = GENMASK(13, 8), > - /* Bits 14-15 reserved */ > - [Y_MIN_LIM] = GENMASK(21, 16), > - /* Bits 22-23 reserved */ > - [Y_MAX_LIM] = GENMASK(29, 24), > - /* Bits 30-31 reserved */ > + [X_MIN_LIM] = GENMASK(7, 0), > + [X_MAX_LIM] = GENMASK(15, 8), > + [Y_MIN_LIM] = GENMASK(23, 16), > + [Y_MAX_LIM] = GENMASK(31, 24), > }; > > IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, > 0x00000400, 0x0020); > > static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { > - [X_MIN_LIM] = GENMASK(5, 0), > - /* Bits 6-7 reserved */ > - [X_MAX_LIM] = GENMASK(13, 8), > - /* Bits 14-15 reserved */ > - [Y_MIN_LIM] = GENMASK(21, 16), > - /* Bits 22-23 reserved */ > - [Y_MAX_LIM] = GENMASK(29, 24), > - /* Bits 30-31 reserved */ > + [X_MIN_LIM] = GENMASK(7, 0), > + [X_MAX_LIM] = GENMASK(15, 8), > + [Y_MIN_LIM] = GENMASK(23, 16), > + [Y_MAX_LIM] = GENMASK(31, 24), > }; > > IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, > 0x00000404, 0x0020); > > static const u32 ipa_reg_src_rsrc_grp_45_rsrc_type_fmask[] = { > - [X_MIN_LIM] = GENMASK(5, 0), > - /* Bits 6-7 reserved */ > - [X_MAX_LIM] = GENMASK(13, 8), > - /* Bits 14-15 reserved */ > - [Y_MIN_LIM] = GENMASK(21, 16), > - /* Bits 22-23 reserved */ > - [Y_MAX_LIM] = GENMASK(29, 24), > - /* Bits 30-31 reserved */ > + [X_MIN_LIM] = GENMASK(7, 0), > + [X_MAX_LIM] = GENMASK(15, 8), > + [Y_MIN_LIM] = GENMASK(23, 16), > + [Y_MAX_LIM] = GENMASK(31, 24), > }; > > IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type, > 0x00000408, 0x0020); > > static const u32 ipa_reg_src_rsrc_grp_67_rsrc_type_fmask[] = { > - [X_MIN_LIM] = GENMASK(5, 0), > - /* Bits 6-7 reserved */ > - [X_MAX_LIM] = GENMASK(13, 8), > - /* Bits 14-15 reserved */ > - [Y_MIN_LIM] = GENMASK(21, 16), > - /* Bits 22-23 reserved */ > - [Y_MAX_LIM] = GENMASK(29, 24), > - /* Bits 30-31 reserved */ > + [X_MIN_LIM] = GENMASK(7, 0), > + [X_MAX_LIM] = GENMASK(15, 8), > + [Y_MIN_LIM] = GENMASK(23, 16), > + [Y_MAX_LIM] = GENMASK(31, 24), > }; > > IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type, > 0x0000040c, 0x0020); > > static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { > - [X_MIN_LIM] = GENMASK(5, 0), > - /* Bits 6-7 reserved */ > - [X_MAX_LIM] = GENMASK(13, 8), > - /* Bits 14-15 reserved */ > - [Y_MIN_LIM] = GENMASK(21, 16), > - /* Bits 22-23 reserved */ > - [Y_MAX_LIM] = GENMASK(29, 24), > - /* Bits 30-31 reserved */ > + [X_MIN_LIM] = GENMASK(7, 0), > + [X_MAX_LIM] = GENMASK(15, 8), > + [Y_MIN_LIM] = GENMASK(23, 16), > + [Y_MAX_LIM] = GENMASK(31, 24), > }; > > IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, > 0x00000500, 0x0020); > > static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { > - [X_MIN_LIM] = GENMASK(5, 0), > - /* Bits 6-7 reserved */ > - [X_MAX_LIM] = GENMASK(13, 8), > - /* Bits 14-15 reserved */ > - [Y_MIN_LIM] = GENMASK(21, 16), > - /* Bits 22-23 reserved */ > - [Y_MAX_LIM] = GENMASK(29, 24), > - /* Bits 30-31 reserved */ > + [X_MIN_LIM] = GENMASK(7, 0), > + [X_MAX_LIM] = GENMASK(15, 8), > + [Y_MIN_LIM] = GENMASK(23, 16), > + [Y_MAX_LIM] = GENMASK(31, 24), > }; > > IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, > 0x00000504, 0x0020); > > static const u32 ipa_reg_dst_rsrc_grp_45_rsrc_type_fmask[] = { > - [X_MIN_LIM] = GENMASK(5, 0), > - /* Bits 6-7 reserved */ > - [X_MAX_LIM] = GENMASK(13, 8), > - /* Bits 14-15 reserved */ > - [Y_MIN_LIM] = GENMASK(21, 16), > - /* Bits 22-23 reserved */ > - [Y_MAX_LIM] = GENMASK(29, 24), > - /* Bits 30-31 reserved */ > + [X_MIN_LIM] = GENMASK(7, 0), > + [X_MAX_LIM] = GENMASK(15, 8), > + [Y_MIN_LIM] = GENMASK(23, 16), > + [Y_MAX_LIM] = GENMASK(31, 24), > }; > > IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type, > 0x00000508, 0x0020); > > static const u32 ipa_reg_dst_rsrc_grp_67_rsrc_type_fmask[] = { > - [X_MIN_LIM] = GENMASK(5, 0), > - /* Bits 6-7 reserved */ > - [X_MAX_LIM] = GENMASK(13, 8), > - /* Bits 14-15 reserved */ > - [Y_MIN_LIM] = GENMASK(21, 16), > - /* Bits 22-23 reserved */ > - [Y_MAX_LIM] = GENMASK(29, 24), > - /* Bits 30-31 reserved */ > + [X_MIN_LIM] = GENMASK(7, 0), > + [X_MAX_LIM] = GENMASK(15, 8), > + [Y_MIN_LIM] = GENMASK(23, 16), > + [Y_MAX_LIM] = GENMASK(31, 24), > }; > > IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type,