From: Tomasz Nowicki <tomasz.nowicki@linaro.org>
To: Bjorn Helgaas <bhelgaas@google.com>
Cc: catalin.marinas@arm.com, will.deacon@arm.com,
lorenzo.pieralisi@arm.com, wangyijing@huawei.com, arnd@arndb.de,
hanjun.guo@linaro.org, Liviu.Dudau@arm.com, tglx@linutronix.de,
mingo@redhat.com, hpa@zytor.com, rjw@rjwysocki.net,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, x86@kernel.org,
linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org,
linaro-acpi@lists.linaro.org
Subject: Re: [PATCH 3/6] x86, acpi, pci: Move PCI config space accessors.
Date: Tue, 17 Feb 2015 14:03:01 +0100 [thread overview]
Message-ID: <54E33C05.9010300@linaro.org> (raw)
In-Reply-To: <20141210231746.GF6692@google.com>
On 11.12.2014 00:17, Bjorn Helgaas wrote:
> On Wed, Nov 19, 2014 at 05:04:48PM +0100, Tomasz Nowicki wrote:
>> We are going to use mmio_config_{} name convention across all architectures.
>
> mmio_config_*() are workarounds for an AMD Fam10h defect [1]. I would prefer
> not to extend these names to other architectures, because they should be
> able to use readb()/writeb()/etc. directly, as we did on x86 before
> 3320ad994afb ("x86: Work around mmio config space quirk on AMD Fam10h").
>
> In fact, it would be nice if we could use readb()/writeb()/etc. on x86, and
> only use mmio_config_*() when we're on AMD Fam10h. Maybe there could be a
> "struct pci_raw_ops pci_mmcfg_amd_fam10h" that used mmio_config_*(), and we
> could set raw_pci_ext_ops to those ops instead of the default ones when
> we're on AMD Fam10h. Then x86 should be able to use the generic
> readb()-based ops on most platforms.
While I do agree we should use readb()/writeb()... methods, I am not
sure there is a nice way to use mmio_config_*() exclusively for AMD
Fam10h. For x86, right now, we have three PCI config accessors sets:
mmconfig_32.c, mmconfig_64.c, numachip.c and each are different. So one
pci_mmcfg_amd_fam10h pci_raw_ops is not enough. I am thinking of having
additional structure (integrated with "struct pci_mmcfg_region") that
keeps MMIO accessors where readb()/writeb() would be the default one.
For AMD Fam10h case we could tweak it as necessary. What do you thing Bjorn?
Tomasz
>
> Bjorn
>
> [1] 3320ad994afb ("x86: Work around mmio config space quirk on AMD Fam10h")
>
> Somewhere in this process, I'd like to update the AMD Fam10h comment to fix
> the typos and reference the spec that talks about this, i.e., the "BIOS and
> Kernel Developer's Guide (BKDG) For AMD Family 10h Processors," rev 3.48,
> sec 2.11.1, "MMIO Configuration Coding Requirements."
>
> That can be a separate patch since it's only cosmetic.
>
>> Currently it belongs to asm/pci_x86.h header which should be included
>> only for x86 specific files. From now on, those accessors are in asm/pci.h
>> header which can be included in non-architecture code much easier.
>>
>> Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
>> Tested-by: Hanjun Guo <hanjun.guo@linaro.org>
>> ---
>> arch/x86/include/asm/pci.h | 42 +++++++++++++++++++++++++++++++++++++++++
>> arch/x86/include/asm/pci_x86.h | 43 ------------------------------------------
>> 2 files changed, 42 insertions(+), 43 deletions(-)
>>
>> diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
>> index 0892ea0..5ba3720 100644
>> --- a/arch/x86/include/asm/pci.h
>> +++ b/arch/x86/include/asm/pci.h
>> @@ -71,6 +71,48 @@ void pcibios_set_master(struct pci_dev *dev);
>> struct irq_routing_table *pcibios_get_irq_routing_table(void);
>> int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
>>
>> +/*
>> + * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
>> + * on their northbrige except through the * %eax register. As such, you MUST
>> + * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
>> + * accessor functions.
>> + * In fact just use pci_config_*, nothing else please.
>> + */
>> +static inline unsigned char mmio_config_readb(void __iomem *pos)
>> +{
>> + u8 val;
>> + asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
>> + return val;
>> +}
>> +
>> +static inline unsigned short mmio_config_readw(void __iomem *pos)
>> +{
>> + u16 val;
>> + asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
>> + return val;
>> +}
>> +
>> +static inline unsigned int mmio_config_readl(void __iomem *pos)
>> +{
>> + u32 val;
>> + asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
>> + return val;
>> +}
>> +
>> +static inline void mmio_config_writeb(void __iomem *pos, u8 val)
>> +{
>> + asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
>> +}
>> +
>> +static inline void mmio_config_writew(void __iomem *pos, u16 val)
>> +{
>> + asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
>> +}
>> +
>> +static inline void mmio_config_writel(void __iomem *pos, u32 val)
>> +{
>> + asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
>> +}
>>
>> #define HAVE_PCI_MMAP
>> extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
>> diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h
>> index caba141..42e7332 100644
>> --- a/arch/x86/include/asm/pci_x86.h
>> +++ b/arch/x86/include/asm/pci_x86.h
>> @@ -121,49 +121,6 @@ extern int __init pcibios_init(void);
>> extern int pci_legacy_init(void);
>> extern void pcibios_fixup_irqs(void);
>>
>> -/*
>> - * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
>> - * on their northbrige except through the * %eax register. As such, you MUST
>> - * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
>> - * accessor functions.
>> - * In fact just use pci_config_*, nothing else please.
>> - */
>> -static inline unsigned char mmio_config_readb(void __iomem *pos)
>> -{
>> - u8 val;
>> - asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
>> - return val;
>> -}
>> -
>> -static inline unsigned short mmio_config_readw(void __iomem *pos)
>> -{
>> - u16 val;
>> - asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
>> - return val;
>> -}
>> -
>> -static inline unsigned int mmio_config_readl(void __iomem *pos)
>> -{
>> - u32 val;
>> - asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
>> - return val;
>> -}
>> -
>> -static inline void mmio_config_writeb(void __iomem *pos, u8 val)
>> -{
>> - asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
>> -}
>> -
>> -static inline void mmio_config_writew(void __iomem *pos, u16 val)
>> -{
>> - asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
>> -}
>> -
>> -static inline void mmio_config_writel(void __iomem *pos, u32 val)
>> -{
>> - asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
>> -}
>> -
>> #ifdef CONFIG_PCI
>> # ifdef CONFIG_ACPI
>> # define x86_default_pci_init pci_acpi_init
>> --
>> 1.9.1
>>
next prev parent reply other threads:[~2015-02-17 13:03 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-19 16:04 [PATCH 0/6] PCI: MMCONFIG clean up Tomasz Nowicki
2014-11-19 16:04 ` [PATCH 1/6] x86, acpi, pci: Reorder logic of pci_mmconfig_insert() function Tomasz Nowicki
2014-11-19 16:04 ` [PATCH 2/6] x86, acpi, pci: Move arch-agnostic MMCFG code out of arch/x86/ directory Tomasz Nowicki
2014-12-10 23:35 ` Bjorn Helgaas
2014-12-10 23:55 ` Bjorn Helgaas
2014-12-12 14:55 ` [Linaro-acpi] " Arnd Bergmann
2014-11-19 16:04 ` [PATCH 3/6] x86, acpi, pci: Move PCI config space accessors Tomasz Nowicki
2014-12-10 23:17 ` Bjorn Helgaas
2015-02-03 9:30 ` Tomasz Nowicki
2015-02-17 13:03 ` Tomasz Nowicki [this message]
2015-02-18 18:27 ` Bjorn Helgaas
2015-02-18 19:02 ` Rob Herring
2014-11-19 16:04 ` [PATCH 4/6] x86, acpi, pci: mmconfig_{32,64}.c code refactoring - remove code duplication Tomasz Nowicki
2014-11-19 16:04 ` [PATCH 5/6] x86, acpi, pci: mmconfig_64.c becomes default implementation for arch agnostic low-level direct PCI config space accessors via MMCONFIG Tomasz Nowicki
2014-11-19 16:04 ` [PATCH 6/6] pci, acpi: Share ACPI PCI config space accessors Tomasz Nowicki
2014-11-19 16:19 ` Arnd Bergmann
2014-11-19 16:24 ` Tomasz Nowicki
2014-11-20 22:26 ` Bjorn Helgaas
2014-11-21 4:00 ` Myron Stowe
2014-11-21 12:24 ` Arnd Bergmann
2014-11-21 18:08 ` Bjorn Helgaas
2014-11-24 10:41 ` Arnd Bergmann
2014-12-08 7:13 ` Tomasz Nowicki
2014-12-09 21:50 ` Bjorn Helgaas
2014-12-10 6:16 ` Tomasz Nowicki
2015-02-02 20:42 ` [PATCH 0/6] PCI: MMCONFIG clean up Bjorn Helgaas
2015-02-03 7:42 ` Tomasz Nowicki
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