From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754647AbbCEIW1 (ORCPT ); Thu, 5 Mar 2015 03:22:27 -0500 Received: from szxga03-in.huawei.com ([119.145.14.66]:8587 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752207AbbCEIW0 (ORCPT ); Thu, 5 Mar 2015 03:22:26 -0500 Message-ID: <54F81223.8090107@huawei.com> Date: Thu, 5 Mar 2015 16:21:55 +0800 From: Hanjun Guo User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.0.1 MIME-Version: 1.0 To: Thomas Gleixner , Will Deacon CC: Catalin Marinas , "Rafael J. Wysocki" , Olof Johansson , Grant Likely , Lorenzo Pieralisi , Arnd Bergmann , Mark Rutland , "Graeme Gregory" , Sudeep Holla , "Jon Masters" , Marc Zyngier , Mark Brown , Robert Richter , Timur Tabi , Ashwin Chaugule , , , , , , Tomasz Nowicki , Jason Cooper , Hanjun Guo Subject: Re: [PATCH v9 16/21] irqchip: Add GICv2 specific ACPI boot support References: <1424853601-6675-1-git-send-email-hanjun.guo@linaro.org> <1424853601-6675-17-git-send-email-hanjun.guo@linaro.org> In-Reply-To: <1424853601-6675-17-git-send-email-hanjun.guo@linaro.org> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.177.17.188] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.54F8123A.00FD,ss=1,re=0.001,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 20f51b153ec27372bc23928dccfe6927 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2015/2/25 16:39, Hanjun Guo wrote: > From: Tomasz Nowicki > > ACPI kernel uses MADT table for proper GIC initialization. It needs to > parse GIC related subtables, collect CPU interface and distributor > addresses and call driver initialization function (which is hardware > abstraction agnostic). In a similar way, FDT initialize GICv1/2. > > NOTE: This commit allow to initialize GICv1/2 basic functionality. > While now simple GICv2 init call is used, any further GIC features > require generic infrastructure for proper ACPI irqchip initialization. > That mechanism and stacked irqdomains to support GICv2 MSI/virtualization > extension, GICv3/4 and its ITS are considered as next steps. > > CC: Jason Cooper > CC: Marc Zyngier > CC: Thomas Gleixner Hi Thomas, Any comments for this patch and the following one "[PATCH v9 17/21] clocksource / arch_timer: Parse GTDT to initialize arch timer" ? If it is ok for you, could you please ACK those two patches, Catalin needs your ACK before it's merged via ARM64 tree. Thanks Hanjun > Tested-by: Suravee Suthikulpanit > Tested-by: Yijing Wang > Tested-by: Mark Langsdorf > Tested-by: Jon Masters > Tested-by: Timur Tabi > Tested-by: Robert Richter > Acked-by: Robert Richter > Signed-off-by: Tomasz Nowicki > Signed-off-by: Hanjun Guo > --- > arch/arm64/include/asm/acpi.h | 2 + > arch/arm64/kernel/acpi.c | 25 +++++++++ > drivers/irqchip/irq-gic.c | 102 +++++++++++++++++++++++++++++++++++ > drivers/irqchip/irqchip.c | 3 ++ > include/linux/acpi.h | 14 +++++ > include/linux/irqchip/arm-gic-acpi.h | 29 ++++++++++ > 6 files changed, 175 insertions(+) > create mode 100644 include/linux/irqchip/arm-gic-acpi.h > > diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h > index 9a23369..a720a61 100644 > --- a/arch/arm64/include/asm/acpi.h > +++ b/arch/arm64/include/asm/acpi.h > @@ -13,6 +13,8 @@ > #define _ASM_ACPI_H > > #include > +#include > + > #include > #include > > diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c > index 31f080e..af308c3 100644 > --- a/arch/arm64/kernel/acpi.c > +++ b/arch/arm64/kernel/acpi.c > @@ -359,3 +359,28 @@ void __init acpi_boot_table_init(void) > pr_err("Can't find FADT\n"); > } > } > + > +void __init acpi_gic_init(void) > +{ > + struct acpi_table_header *table; > + acpi_status status; > + acpi_size tbl_size; > + int err; > + > + if (acpi_disabled) > + return; > + > + status = acpi_get_table_with_size(ACPI_SIG_MADT, 0, &table, &tbl_size); > + if (ACPI_FAILURE(status)) { > + const char *msg = acpi_format_exception(status); > + > + pr_err("Failed to get MADT table, %s\n", msg); > + return; > + } > + > + err = gic_v2_acpi_init(table); > + if (err) > + pr_err("Failed to initialize GIC IRQ controller"); > + > + early_acpi_os_unmap_memory((char *)table, tbl_size); > +} > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c > index 4634cf7..929d668 100644 > --- a/drivers/irqchip/irq-gic.c > +++ b/drivers/irqchip/irq-gic.c > @@ -33,12 +33,14 @@ > #include > #include > #include > +#include > #include > #include > #include > #include > #include > #include > +#include > > #include > #include > @@ -1086,3 +1088,103 @@ IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); > IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); > > #endif > + > +#ifdef CONFIG_ACPI > +static phys_addr_t dist_phy_base, cpu_phy_base __initdata; > + > +static int __init > +gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, > + const unsigned long end) > +{ > + struct acpi_madt_generic_interrupt *processor; > + phys_addr_t gic_cpu_base; > + static int cpu_base_assigned; > + > + processor = (struct acpi_madt_generic_interrupt *)header; > + > + if (BAD_MADT_ENTRY(processor, end)) > + return -EINVAL; > + > + /* > + * There is no support for non-banked GICv1/2 register in ACPI spec. > + * All CPU interface addresses have to be the same. > + */ > + gic_cpu_base = processor->base_address; > + if (cpu_base_assigned && gic_cpu_base != cpu_phy_base) > + return -EINVAL; > + > + cpu_phy_base = gic_cpu_base; > + cpu_base_assigned = 1; > + return 0; > +} > + > +static int __init > +gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header, > + const unsigned long end) > +{ > + struct acpi_madt_generic_distributor *dist; > + > + dist = (struct acpi_madt_generic_distributor *)header; > + > + if (BAD_MADT_ENTRY(dist, end)) > + return -EINVAL; > + > + dist_phy_base = dist->base_address; > + return 0; > +} > + > +int __init > +gic_v2_acpi_init(struct acpi_table_header *table) > +{ > + void __iomem *cpu_base, *dist_base; > + int count; > + > + /* Collect CPU base addresses */ > + count = acpi_parse_entries(ACPI_SIG_MADT, > + sizeof(struct acpi_table_madt), > + gic_acpi_parse_madt_cpu, table, > + ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0); > + if (count <= 0) { > + pr_err("No valid GICC entries exist\n"); > + return -EINVAL; > + } > + > + /* > + * Find distributor base address. We expect one distributor entry since > + * ACPI 5.1 spec neither support multi-GIC instances nor GIC cascade. > + */ > + count = acpi_parse_entries(ACPI_SIG_MADT, > + sizeof(struct acpi_table_madt), > + gic_acpi_parse_madt_distributor, table, > + ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0); > + if (count <= 0) { > + pr_err("No valid GICD entries exist\n"); > + return -EINVAL; > + } else if (count > 1) { > + pr_err("More than one GICD entry detected\n"); > + return -EINVAL; > + } > + > + cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE); > + if (!cpu_base) { > + pr_err("Unable to map GICC registers\n"); > + return -ENOMEM; > + } > + > + dist_base = ioremap(dist_phy_base, ACPI_GICV2_DIST_MEM_SIZE); > + if (!dist_base) { > + pr_err("Unable to map GICD registers\n"); > + iounmap(cpu_base); > + return -ENOMEM; > + } > + > + /* > + * Initialize zero GIC instance (no multi-GIC support). Also, set GIC > + * as default IRQ domain to allow for GSI registration and GSI to IRQ > + * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()). > + */ > + gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL); > + irq_set_default_host(gic_data[0].domain); > + return 0; > +} > +#endif > diff --git a/drivers/irqchip/irqchip.c b/drivers/irqchip/irqchip.c > index 0fe2f71..5855240 100644 > --- a/drivers/irqchip/irqchip.c > +++ b/drivers/irqchip/irqchip.c > @@ -8,6 +8,7 @@ > * warranty of any kind, whether express or implied. > */ > > +#include > #include > #include > #include > @@ -26,4 +27,6 @@ extern struct of_device_id __irqchip_of_table[]; > void __init irqchip_init(void) > { > of_irq_init(__irqchip_of_table); > + > + acpi_irq_init(); > } > diff --git a/include/linux/acpi.h b/include/linux/acpi.h > index c03d8d1..e27117a 100644 > --- a/include/linux/acpi.h > +++ b/include/linux/acpi.h > @@ -557,6 +557,20 @@ static inline int acpi_device_modalias(struct device *dev, > > #endif /* !CONFIG_ACPI */ > > +#if defined(CONFIG_ACPI) && defined(CONFIG_ARM64) > +static inline void acpi_irq_init(void) > +{ > + /* > + * Hardcode ACPI IRQ chip initialization to GICv2 for now. > + * Proper irqchip infrastructure will be implemented along with > + * incoming GICv2m|GICv3|ITS bits. > + */ > + acpi_gic_init(); > +} > +#else > +static inline void acpi_irq_init(void) { } > +#endif > + > #ifdef CONFIG_ACPI > void acpi_os_set_prepare_sleep(int (*func)(u8 sleep_state, > u32 pm1a_ctrl, u32 pm1b_ctrl)); > diff --git a/include/linux/irqchip/arm-gic-acpi.h b/include/linux/irqchip/arm-gic-acpi.h > new file mode 100644 > index 0000000..d5b2c79 > --- /dev/null > +++ b/include/linux/irqchip/arm-gic-acpi.h > @@ -0,0 +1,29 @@ > +/* > + * Copyright (C) 2014, Linaro Ltd. > + * Author: Tomasz Nowicki > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#ifndef ARM_GIC_ACPI_H_ > +#define ARM_GIC_ACPI_H_ > + > +#ifdef CONFIG_ACPI > + > +/* > + * Hard code here, we can not get memory size from MADT (but FDT does), > + * Actually no need to do that, because this size can be inferred > + * from GIC spec. > + */ > +#define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K) > +#define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) > + > +struct acpi_table_header; > + > +int gic_v2_acpi_init(struct acpi_table_header *table); > +void acpi_gic_init(void); > +#endif > + > +#endif /* ARM_GIC_ACPI_H_ */