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Tue, 8 Jun 2021 10:37:20 +0000 Subject: Re: [PATCH V2 1/5] PCI: tegra: Fix handling BME_CHGED event To: Om Prakash Singh , , , , , , CC: , , , , References: <20210606082204.14222-1-omp@nvidia.com> <20210606082204.14222-2-omp@nvidia.com> From: Vidya Sagar Message-ID: <54fe5d68-9bc9-ce80-3917-49d616802698@nvidia.com> Date: Tue, 8 Jun 2021 16:07:17 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: <20210606082204.14222-2-omp@nvidia.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bd0cfe06-6a77-4e7b-e735-08d92a6966ff X-MS-TrafficTypeDiagnostic: MWHPR1201MB0160: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1751; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jun 2021 10:37:23.5713 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd0cfe06-6a77-4e7b-e735-08d92a6966ff X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT011.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1201MB0160 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Acked-by: Vidya Sagar On 6/6/2021 1:52 PM, Om Prakash Singh wrote: > In tegra_pcie_ep_hard_irq(), APPL_INTR_STATUS_L0 is stored in val and again > APPL_INTR_STATUS_L1_0_0 is also stored in val. So when execution reaches > "if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT)", val is not correct. > > Signed-off-by: Om Prakash Singh > --- > > Changes in V2: > - Update variable naming as per comment from Bjorn Helgaas > > drivers/pci/controller/dwc/pcie-tegra194.c | 30 +++++++++++----------- > 1 file changed, 15 insertions(+), 15 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c > index bafd2c6ab3c2..6f388523bffe 100644 > --- a/drivers/pci/controller/dwc/pcie-tegra194.c > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c > @@ -615,19 +615,19 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) > struct tegra_pcie_dw *pcie = arg; > struct dw_pcie_ep *ep = &pcie->pci.ep; > int spurious = 1; > - u32 val, tmp; > + u32 status_l0, status_l1, link_status; > > - val = appl_readl(pcie, APPL_INTR_STATUS_L0); > - if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) { > - val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0); > - appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0); > + status_l0 = appl_readl(pcie, APPL_INTR_STATUS_L0); > + if (status_l0 & APPL_INTR_STATUS_L0_LINK_STATE_INT) { > + status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0); > + appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0); > > - if (val & APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE) > + if (status_l1 & APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE) > pex_ep_event_hot_rst_done(pcie); > > - if (val & APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED) { > - tmp = appl_readl(pcie, APPL_LINK_STATUS); > - if (tmp & APPL_LINK_STATUS_RDLH_LINK_UP) { > + if (status_l1 & APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED) { > + link_status = appl_readl(pcie, APPL_LINK_STATUS); > + if (link_status & APPL_LINK_STATUS_RDLH_LINK_UP) { > dev_dbg(pcie->dev, "Link is up with Host\n"); > dw_pcie_ep_linkup(ep); > } > @@ -636,11 +636,11 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) > spurious = 0; > } > > - if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) { > - val = appl_readl(pcie, APPL_INTR_STATUS_L1_15); > - appl_writel(pcie, val, APPL_INTR_STATUS_L1_15); > + if (status_l0 & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) { > + status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_15); > + appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_15); > > - if (val & APPL_INTR_STATUS_L1_15_CFG_BME_CHGED) > + if (status_l1 & APPL_INTR_STATUS_L1_15_CFG_BME_CHGED) > return IRQ_WAKE_THREAD; > > spurious = 0; > @@ -648,8 +648,8 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) > > if (spurious) { > dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n", > - val); > - appl_writel(pcie, val, APPL_INTR_STATUS_L0); > + status_l0); > + appl_writel(pcie, status_l0, APPL_INTR_STATUS_L0); > } > > return IRQ_HANDLED; >