From: David Ahern <david.ahern@oracle.com>
To: Yinghai Lu <yinghai@kernel.org>, David Miller <davem@davemloft.net>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"sparclinux@vger.kernel.org" <sparclinux@vger.kernel.org>,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: d63e2e1f3df breaks sparc/T5-8
Date: Mon, 30 Mar 2015 16:54:05 -0600 [thread overview]
Message-ID: <5519D40D.20903@oracle.com> (raw)
In-Reply-To: <CAE9FiQXu8qvCo9Dx6vUBXEO029n8K=c=CGtsfvWMGYdVgqtgOw@mail.gmail.com>
On 3/29/15 2:07 PM, Yinghai Lu wrote:
> [ 286.647560] PCI: scan_bus[/pci@300/pci@1/pci@0/pci@6] bus no 8
> [ 286.921232] PCI: Claiming 0000:00:01.0: Resource 15:
> 0000800100000000..00008004afffffff [220c]
> [ 287.229190] PCI: Claiming 0000:01:00.0: Resource 15:
> 0000800100000000..00008004afffffff [220c]
> [ 287.533428] PCI: Claiming 0000:02:04.0: Resource 15:
> 0000800100000000..000080012fffffff [220c]
> [ 288.149831] PCI: Claiming 0000:03:00.0: Resource 15:
> 0000800100000000..000080012fffffff [220c]
> [ 288.252466] PCI: Claiming 0000:04:06.0: Resource 14:
> 0000800100000000..000080010fffffff [220c]
> [ 288.867196] PCI: Claiming 0000:05:00.0: Resource 0:
> 0000800100000000..0000800100001fff [204]
> [ 288.968221] pci 0000:05:00.0: can't claim BAR 0 [mem
> 0x800100000000-0x800100001fff]: no compatible bridge window
>
> the bridge resource has IORESOURCE_PREFETCH, but the device doesn't have that.
>
> So pci_claim_resource can not find parent resource for device
> resource: we can not
> put non pref mem under pref mem.
>
> Can you send out result from ?
> lspci -vvxxx -s 0000:05:00.0
# lspci -vvxxx -s 0000:05:00.0
0000:05:00.0 USB controller: Renesas Technology Corp. uPD720201 USB 3.0
Host Controller (rev 03) (prog-if 30 [XHCI])
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 00000004
Region 0: Memory at 100000000 (64-bit, non-prefetchable) [size=8K]
Region 2: [virtual] Memory at ffff800000000000 (32-bit, non-prefetchable)
Region 3: [virtual] Memory at ffff800000000000 (32-bit, non-prefetchable)
Region 4: [virtual] Memory at ffff800000000000 (32-bit, non-prefetchable)
Region 5: [virtual] Memory at ffff800000000000 (32-bit, non-prefetchable)
[virtual] Expansion ROM at ffff800000000000 [disabled]
Capabilities: [50] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA
PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [70] MSI: Enable- Count=1/8 Maskable- 64bit+
Address: 0000000000000000 Data: 0000
Capabilities: [90] MSI-X: Enable+ Count=8 Masked-
Vector table: BAR=0 offset=00001000
PBA: BAR=0 offset=00001080
Capabilities: [a0] Express (v2) Endpoint, MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1
unlimited
ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend-
LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <4us,
L1 unlimited
ClockPM+ Surprise- LLActRep- BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive-
BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR+, OBFF
Not Supported
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF
Disabled
LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance-
ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-,
EqualizationPhase1-
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
Capabilities: [100 v1] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF-
MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF-
MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+
MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
Capabilities: [150 v1] Latency Tolerance Reporting
Max snoop latency: 0ns
Max no snoop latency: 0ns
Kernel driver in use: xhci_hcd
00: 12 19 14 00 06 04 10 00 03 30 03 0c 10 00 00 00
10: 04 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 00 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 70 c3 c9 08 00 00 00 00 00 00 00 00 00 00 00
60: 30 20 00 00 00 00 00 00 00 00 00 00 09 18 20 00
70: 05 90 86 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 11 a0 07 80 00 10 00 00 80 10 00 00 00 00 00 00
a0: 10 00 02 00 c0 8f 00 00 00 28 19 00 12 ec 07 00
b0: 00 00 12 10 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 10 08 00 00 00 00 00 00 00 00 00 00
d0: 02 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 55 00 00 00 01 05 10 20 20 00
f0: 50 07 00 00 00 00 00 80 00 00 00 00 00 00 00 00
>
> If it does have pref, could be of device layer does not pass the pref
> flag properly
> via pci_parse_of_addrs/of_get_property(node, "assigned-addresses".
>
> or the addr0 from "ranges" and "assigned-address" has different definition.
>
> Thanks
>
> Yinghai
>
next prev parent reply other threads:[~2015-03-30 22:54 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-26 16:51 d63e2e1f3df breaks sparc/T5-8 David Ahern
2015-03-26 20:43 ` Yinghai Lu
2015-03-26 23:27 ` David Ahern
2015-03-27 21:01 ` Yinghai Lu
2015-03-27 21:50 ` David Miller
2015-03-27 22:51 ` Yinghai Lu
[not found] ` <CABhMZUVqgsYdT4wn2H8hsrh4f=6hT0G+sg=wwYSt33+jtvBS9A@mail.gmail.com>
2015-03-29 18:32 ` David Miller
2015-04-03 15:45 ` Bjorn Helgaas
2015-04-03 16:48 ` David Miller
2015-03-27 23:57 ` Yinghai Lu
2015-03-28 0:32 ` David Ahern
2015-03-28 0:36 ` David Ahern
2015-03-28 3:19 ` Yinghai Lu
2015-03-28 3:22 ` David Ahern
2015-03-28 3:27 ` Yinghai Lu
2015-03-28 3:45 ` David Ahern
2015-03-28 5:26 ` Yinghai Lu
2015-03-28 14:48 ` David Ahern
2015-03-28 20:24 ` Yinghai Lu
2015-03-29 14:47 ` David Ahern
2015-03-29 20:07 ` Yinghai Lu
2015-03-30 22:54 ` David Ahern [this message]
2015-03-31 1:06 ` Yinghai Lu
2015-03-31 4:10 ` David Ahern
2015-03-31 16:53 ` Yinghai Lu
2015-03-31 17:04 ` David Ahern
2015-03-31 20:28 ` Yinghai Lu
2015-03-31 22:29 ` David Ahern
2015-03-31 22:38 ` Yinghai Lu
2015-03-31 22:42 ` David Ahern
2015-03-31 15:06 ` David Miller
2015-03-31 18:16 ` Yinghai Lu
2015-03-31 18:19 ` David Miller
2015-03-31 18:25 ` Yinghai Lu
2015-03-28 1:05 ` Sam Ravnborg
2015-03-28 2:07 ` Yinghai Lu
2015-03-28 8:18 ` Sam Ravnborg
2015-03-28 18:16 ` David Miller
2015-03-28 20:19 ` Yinghai Lu
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