From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932844AbbDNQMV (ORCPT ); Tue, 14 Apr 2015 12:12:21 -0400 Received: from mail-bl2on0099.outbound.protection.outlook.com ([65.55.169.99]:34883 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932136AbbDNQMO (ORCPT ); Tue, 14 Apr 2015 12:12:14 -0400 Authentication-Results: spf=fail (sender IP is 66.35.236.236) smtp.mailfrom=opensource.altera.com; vger.kernel.org; dkim=none (message not signed) header.d=none; Message-ID: <552D3B24.501@opensource.altera.com> Date: Tue, 14 Apr 2015 11:07:00 -0500 From: Dinh Nguyen User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.0 MIME-Version: 1.0 To: , CC: , , , , , , , , Subject: Re: [PATCH 0/3] clk: socfpga: Add clock driver for Arria10 References: <1428036055-27607-1-git-send-email-dinguyen@opensource.altera.com> In-Reply-To: <1428036055-27607-1-git-send-email-dinguyen@opensource.altera.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: BLUPR08CA0042.namprd08.prod.outlook.com (10.141.200.22) To BY1PR03MB1370.namprd03.prod.outlook.com (25.162.109.28) Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY1PR03MB1370;UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY1PR0301MB1192; X-Forefront-Antispam-Report-Untrusted: BMV:1;SFV:NSPM;SFS:(10009020)(6049001)(6009001)(51704005)(479174004)(164054003)(377454003)(87976001)(65806001)(83506001)(47776003)(77156002)(66066001)(122386002)(50466002)(62966003)(2950100001)(64126003)(40100003)(65956001)(4001350100001)(92566002)(54356999)(50986999)(42186005)(19580395003)(86362001)(65816999)(76176999)(33656002)(46102003)(4001410100001)(19580405001);DIR:OUT;SFP:1101;SCL:1;SRVR:BY1PR03MB1370;H:[137.57.160.210];FPR:;SPF:None;MLV:sfv;LANG:en; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:;UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5002010)(5005006);SRVR:BY1PR03MB1370;BCL:0;PCL:0;RULEID:;SRVR:BY1PR03MB1370;BCL:0;PCL:0;RULEID:(601004)(5002010)(5005006);SRVR:BY1PR0301MB1192;BCL:0;PCL:0;RULEID:;SRVR:BY1PR0301MB1192; X-Forefront-PRVS: 054642504A X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR03MB1370 X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: BN1AFFO11FD045.protection.gbl X-Forefront-Antispam-Report: CIP:66.35.236.236;CTRY:US;IPV:NLI;EFV:NLI;BMV:1;SFV:NSPM;SFS:(10009020)(6009001)(339900001)(164054003)(189002)(24454002)(199003)(51704005)(377454003)(479174004)(92566002)(62966003)(46102003)(19580405001)(6806004)(83506001)(40100003)(4001540100001)(16796002)(4001350100001)(2950100001)(33656002)(106466001)(85426001)(87936001)(105606002)(54356999)(65806001)(66066001)(86362001)(47776003)(77156002)(65816999)(64126003)(65956001)(23746002)(122386002)(50466002)(19580395003)(4001410100001)(90366008)(76176999)(50986999)(7099027);DIR:OUT;SFP:1101;SCL:1;SRVR:BY1PR0301MB1192;H:sj-itexedge04.altera.priv.altera.com;FPR:;SPF:Fail;MLV:ovrnspm;MX:1;A:0;PTR:InfoDomainNonexistent;LANG:en; X-Forefront-PRVS: 054642504A X-OriginatorOrg: opensource.altera.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2015 16:12:11.8522 (UTC) X-MS-Exchange-CrossTenant-Id: fbd72e03-d4a5-4110-adce-614d51f2077a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fbd72e03-d4a5-4110-adce-614d51f2077a;Ip=[66.35.236.236];Helo=[sj-itexedge04.altera.priv.altera.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0301MB1192 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Mike, Stephen, On 04/02/2015 11:40 PM, dinguyen@opensource.altera.com wrote: > From: Dinh Nguyen > > Hi, > > This patch series add the clock driver for the Arria10 platform. Although the > Arria10 SoC's clock framework has some similarities the Cyclone/Arria 5, the > differences are enough to warrant it's own driver, rather than polluting the > existing driver with platform lookups. > > Dinh Nguyen (3): > clk: socfpga: update clk.h so for Arria10 platform to use > clk: socfpga: add a clock driver for the Arria 10 platform > ARM: socfpga: dts: add clocks to the Arria10 platform > > arch/arm/boot/dts/socfpga_arria10.dtsi | 298 ++++++++++++++++++++++++++++++++- > drivers/clk/socfpga/Makefile | 1 + > drivers/clk/socfpga/clk-gate-a10.c | 187 +++++++++++++++++++++ > drivers/clk/socfpga/clk-gate.c | 4 - > drivers/clk/socfpga/clk-periph-a10.c | 131 +++++++++++++++ > drivers/clk/socfpga/clk-pll-a10.c | 132 +++++++++++++++ > drivers/clk/socfpga/clk.c | 7 +- > drivers/clk/socfpga/clk.h | 10 +- > 8 files changed, 760 insertions(+), 10 deletions(-) > create mode 100644 drivers/clk/socfpga/clk-gate-a10.c > create mode 100644 drivers/clk/socfpga/clk-periph-a10.c > create mode 100644 drivers/clk/socfpga/clk-pll-a10.c > Just wondering if you have had a chance to look over this patch series? Thanks, Dinh