From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932611AbbIDMAS (ORCPT ); Fri, 4 Sep 2015 08:00:18 -0400 Received: from eu-smtp-delivery-143.mimecast.com ([207.82.80.143]:40430 "EHLO eu-smtp-delivery-143.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751939AbbIDMAR convert rfc822-to-8bit (ORCPT ); Fri, 4 Sep 2015 08:00:17 -0400 Message-ID: <55E987CA.4090302@arm.com> Date: Fri, 04 Sep 2015 13:00:10 +0100 From: "Suzuki K. Poulose" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: Alexander Kuleshov , Catalin Marinas , Will Deacon CC: "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH 1/3] arm64/cpufeature.h: Add macros for a cpu features testing References: <1441303911-9421-1-git-send-email-kuleshovmail@gmail.com> In-Reply-To: <1441303911-9421-1-git-send-email-kuleshovmail@gmail.com> X-OriginalArrivalTime: 04 Sep 2015 12:00:10.0675 (UTC) FILETIME=[3FE9C030:01D0E709] X-MC-Unique: MXaFgNmsQTCEP-beGwmRkw-1 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 03/09/15 19:11, Alexander Kuleshov wrote: > This patch provides a couple of macros for the testing of processor > features (crypto and FP/SIMD) like support of SHA1, AES instructions, > support for FPU and etc. There is already a couple of places in the > arch/arm64/kernel where these processor features are tested and these > macros are facilitate this. > > Signed-off-by: Alexander Kuleshov > --- > arch/arm64/include/asm/cpufeature.h | 44 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h > index c104421..2919455 100644 > --- a/arch/arm64/include/asm/cpufeature.h > +++ b/arch/arm64/include/asm/cpufeature.h > @@ -28,7 +28,50 @@ > > #define ARM64_NCAPS 4 > > +/* > + * ID_AA64ISAR0_EL1 AES, bits [7:4] > + */ > +#define ID_AA64ISAR0_EL1_AES_MASK 4 > +#define ID_AA64ISAR0_EL1_AES(feature) \ > + (((feature >> ID_AA64ISAR0_EL1_AES_MASK) & 0xf) & 1UL) > +#define ID_AA64ISAR0_EL1_PMULL(feature) \ > + (((feature >> ID_AA64ISAR0_EL1_AES_MASK) & 0xf) & 2UL) > + There is generic CPUID feature helper queued for 4.3, which can extract the feature bits cpuid_feature_extract_field(feature, shift) You might want to use it instead. Btw, I have a patch series(waiting for the merge window, before I post), which changes the way we initialise the HWCAP bits. Thanks Suzuki