From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932616AbbIXDcM (ORCPT ); Wed, 23 Sep 2015 23:32:12 -0400 Received: from regular1.263xmail.com ([211.150.99.138]:40809 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932250AbbIXDcK (ORCPT ); Wed, 23 Sep 2015 23:32:10 -0400 X-263anti-spam: KSV:0;BIG:0;ABS:1;DNS:0;ATT:0;SPF:S; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 1 X-SKE-CHECKED: 1 X-ADDR-CHECKED: 0 X-RL-SENDER: zhengxing@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zhengxing@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Message-ID: <56036EAE.9040201@rock-chips.com> Date: Thu, 24 Sep 2015 11:31:58 +0800 From: Xing Zheng User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:11.0) Gecko/20120410 Thunderbird/11.0.1 MIME-Version: 1.0 To: =?UTF-8?B?SGVpa28gU3TDvGJuZXI=?= CC: linux-rockchip@lists.infradead.org, Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036 References: <1442478540-15068-1-git-send-email-zhengxing@rock-chips.com> <1442478540-15068-4-git-send-email-zhengxing@rock-chips.com> <1775899.zcIuq65f1o@diego> <5603683F.4020302@rock-chips.com> In-Reply-To: <5603683F.4020302@rock-chips.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2015年09月24日 11:04, Xing Zheng wrote: >>> >>> #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \ >>> @@ -95,12 +106,31 @@ enum rockchip_pll_type { >>> .nb = _nb, \ >>> } >>> >>> +#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ >>> + _postdiv2, _dsmpd, _frac) \ >>> +{ \ >>> + .rate = _rate##U, \ >>> + .fbdiv = _fbdiv, \ >>> + .postdiv1 = _postdiv1, \ >>> + .refdiv = _refdiv, \ >>> + .postdiv2 = _postdiv2, \ >>> + .dsmpd = _dsmpd, \ >>> + .frac = _frac, \ >>> +} >>> + >>> struct rockchip_pll_rate_table { >>> unsigned long rate; >>> unsigned int nr; >>> unsigned int nf; >>> unsigned int no; >>> unsigned int nb; >>> + /* for RK3036 */ >>> + unsigned int fbdiv; >>> + unsigned int postdiv1; >>> + unsigned int refdiv; >>> + unsigned int postdiv2; >>> + unsigned int dsmpd; >>> + unsigned int frac; >> same for these 2 ... should be part of the pll addition itself > }; > Done. > Sorry, I have one question: The "struct rockchip_pll_rate_table" is called in "rockchip/clk-pll.c" on many functions, I think I could add a struct like: struct rk3036_pll_rate_table { unsigned int fbdiv; unsigned int postdiv1; unsigned int refdiv; unsigned int postdiv2; unsigned int dsmpd; unsigned int frac; }; but, it will add many redundancy codes in "rockchip/clk-pll.c" just for call "struct rk3036_pll_rate_table". Thanks.