From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966826AbdDZTda (ORCPT ); Wed, 26 Apr 2017 15:33:30 -0400 Received: from plaes.org ([188.166.43.21]:56213 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966808AbdDZTcn (ORCPT ); Wed, 26 Apr 2017 15:32:43 -0400 From: Priit Laes To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Philipp Zabel , Russell King , Chen-Yu Tsai , Maxime Ripard , Mark Rutland , Rob Herring , Stephen Boyd , Michael Turquette , linux-sunxi@googlegroups.com, Priit Laes Subject: [PATCH v3 4/5] ARM: sun7i: Convert to CCU Date: Wed, 26 Apr 2017 22:32:24 +0300 Message-Id: <560676328328d23f344468f5c43ff1b1533f36f0.1493235134.git-series.plaes@plaes.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert sun7i-a20.dtsi to new CCU driver. Tested on Cubietruck. Signed-off-by: Priit Laes --- arch/arm/boot/dts/sun7i-a20.dtsi | 720 +++----------------------------- 1 file changed, 86 insertions(+), 634 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 93aa559..7590cc4 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -47,7 +47,8 @@ #include #include -#include +#include +#include #include / { @@ -66,9 +67,10 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>, <&de_be0_clk>, - <&tcon0_ch1_clk>, <&dram_gates 26>; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>, + <&ccu CLK_HDMI>; status = "disabled"; }; @@ -76,9 +78,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; - clocks = <&ahb_gates 36>, <&ahb_gates 44>, - <&de_be0_clk>, <&tcon0_ch0_clk>, - <&dram_gates 26>; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, + <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>, + <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; @@ -86,10 +88,10 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&ahb_gates 34>, <&ahb_gates 36>, - <&ahb_gates 44>, - <&de_be0_clk>, <&tcon0_ch1_clk>, - <&dram_gates 5>, <&dram_gates 26>; + clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, + <&ccu CLK_AHB_DE_BE0>, + <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>, + <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; }; @@ -102,7 +104,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; - clocks = <&cpu>; + clocks = <&ccu CLK_CPU>; clock-latency = <244144>; /* 8 32k periods */ operating-points = < /* kHz uV */ @@ -183,21 +185,11 @@ osc24M: clk@01c20050 { #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-osc-clk"; - reg = <0x01c20050 0x4>; + compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "osc24M"; }; - osc3M: osc3M_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <8>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "osc3M"; - }; - osc32k: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; @@ -205,528 +197,6 @@ clock-output-names = "osc32k"; }; - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - pll2: clk@01c20008 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll2-clk"; - reg = <0x01c20008 0x8>; - clocks = <&osc24M>; - clock-output-names = "pll2-1x", "pll2-2x", - "pll2-4x", "pll2-8x"; - }; - - pll3: clk@01c20010 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20010 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll3"; - }; - - pll3x2: pll3x2_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&pll3>; - clock-div = <1>; - clock-mult = <2>; - clock-output-names = "pll3-2x"; - }; - - pll4: clk@01c20018 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-pll4-clk"; - reg = <0x01c20018 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll4"; - }; - - pll5: clk@01c20020 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll5-clk"; - reg = <0x01c20020 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll5_ddr", "pll5_other"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6_sata", "pll6_other", "pll6", - "pll6_div_4"; - }; - - pll7: clk@01c20030 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20030 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll7"; - }; - - pll7x2: pll7x2_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&pll7>; - clock-div = <1>; - clock-mult = <2>; - clock-output-names = "pll7-2x"; - }; - - pll8: clk@01c20040 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-pll4-clk"; - reg = <0x01c20040 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll8"; - }; - - cpu: cpu@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; - clock-output-names = "cpu"; - }; - - axi: axi@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-axi-clk"; - reg = <0x01c20054 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - ahb: ahb@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun5i-a13-ahb-clk"; - reg = <0x01c20054 0x4>; - clocks = <&axi>, <&pll6 3>, <&pll6 1>; - clock-output-names = "ahb"; - /* - * Use PLL6 as parent, instead of CPU/AXI - * which has rate changes due to cpufreq - */ - assigned-clocks = <&ahb>; - assigned-clock-parents = <&pll6 3>; - }; - - ahb_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun7i-a20-ahb-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb>; - clock-indices = <0>, <1>, - <2>, <3>, <4>, - <5>, <6>, <7>, <8>, - <9>, <10>, <11>, <12>, - <13>, <14>, <16>, - <17>, <18>, <20>, <21>, - <22>, <23>, <25>, - <28>, <32>, <33>, <34>, - <35>, <36>, <37>, <40>, - <41>, <42>, <43>, - <44>, <45>, <46>, - <47>, <49>, <50>, - <52>; - clock-output-names = "ahb_usb0", "ahb_ehci0", - "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", - "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", - "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", - "ahb_nand", "ahb_sdram", "ahb_ace", - "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", - "ahb_spi2", "ahb_spi3", "ahb_sata", - "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", - "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", - "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", - "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", - "ahb_de_fe1", "ahb_gmac", "ahb_mp", - "ahb_mali"; - }; - - apb0: apb0@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb>; - clock-output-names = "apb0"; - }; - - apb0_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun7i-a20-apb0-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb0>; - clock-indices = <0>, <1>, - <2>, <3>, <4>, - <5>, <6>, <7>, - <8>, <10>; - clock-output-names = "apb0_codec", "apb0_spdif", - "apb0_ac97", "apb0_i2s0", "apb0_i2s1", - "apb0_pio", "apb0_ir0", "apb0_ir1", - "apb0_i2s2", "apb0_keypad"; - }; - - apb1: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&osc32k>; - clock-output-names = "apb1"; - }; - - apb1_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun7i-a20-apb1-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <1>, - <2>, <3>, <4>, - <5>, <6>, <7>, - <15>, <16>, <17>, - <18>, <19>, <20>, - <21>, <22>, <23>; - clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_i2c3", "apb1_can", - "apb1_scr", "apb1_ps20", "apb1_ps21", - "apb1_i2c4", "apb1_uart0", "apb1_uart1", - "apb1_uart2", "apb1_uart3", "apb1_uart4", - "apb1_uart5", "apb1_uart6", "apb1_uart7"; - }; - - nand_clk: clk@01c20080 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20080 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "nand"; - }; - - ms_clk: clk@01c20084 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20084 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ms"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - mmc3_clk: clk@01c20094 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20094 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc3", - "mmc3_output", - "mmc3_sample"; - }; - - ts_clk: clk@01c20098 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20098 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ts"; - }; - - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ss"; - }; - - spi0_clk: clk@01c200a0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi0"; - }; - - spi1_clk: clk@01c200a4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi1"; - }; - - spi2_clk: clk@01c200a8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a8 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi2"; - }; - - pata_clk: clk@01c200ac { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200ac 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "pata"; - }; - - ir0_clk: clk@01c200b0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir0"; - }; - - ir1_clk: clk@01c200b4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir1"; - }; - - i2s0_clk: clk@01c200b8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200b8 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "i2s0"; - }; - - ac97_clk: clk@01c200bc { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200bc 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "ac97"; - }; - - spdif_clk: clk@01c200c0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200c0 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "spdif"; - }; - - keypad_clk: clk@01c200c4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200c4 0x4>; - clocks = <&osc24M>; - clock-output-names = "keypad"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&pll6 1>; - clock-output-names = "usb_ohci0", "usb_ohci1", - "usb_phy"; - }; - - spi3_clk: clk@01c200d4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200d4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi3"; - }; - - i2s1_clk: clk@01c200d8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200d8 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "i2s1"; - }; - - i2s2_clk: clk@01c200dc { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200dc 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "i2s2"; - }; - - dram_gates: clk@01c20100 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-dram-gates-clk"; - reg = <0x01c20100 0x4>; - clocks = <&pll5 0>; - clock-indices = <0>, - <1>, <2>, - <3>, - <4>, - <5>, <6>, - <15>, - <24>, <25>, - <26>, <27>, - <28>, <29>; - clock-output-names = "dram_ve", - "dram_csi0", "dram_csi1", - "dram_ts", - "dram_tvd", - "dram_tve0", "dram_tve1", - "dram_output", - "dram_de_fe1", "dram_de_fe0", - "dram_de_be0", "dram_de_be1", - "dram_de_mp", "dram_ace"; - }; - - de_be0_clk: clk@01c20104 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20104 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be0"; - }; - - de_be1_clk: clk@01c20108 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20108 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be1"; - }; - - de_fe0_clk: clk@01c2010c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c2010c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe0"; - }; - - de_fe1_clk: clk@01c20110 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20110 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe1"; - }; - - tcon0_ch0_clk: clk@01c20118 { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c20118 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon0-ch0-sclk"; - - }; - - tcon1_ch0_clk: clk@01c2011c { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c2011c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon1-ch0-sclk"; - - }; - - tcon0_ch1_clk: clk@01c2012c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c2012c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon0-ch1-sclk"; - - }; - - tcon1_ch1_clk: clk@01c20130 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c20130 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon1-ch1-sclk"; - - }; - - ve_clk: clk@01c2013c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-ve-clk"; - reg = <0x01c2013c 0x4>; - clocks = <&pll4>; - clock-output-names = "ve"; - }; - - codec_clk: clk@01c20140 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-codec-clk"; - reg = <0x01c20140 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "codec"; - }; - - mbus_clk: clk@01c2015c { - #clock-cells = <0>; - compatible = "allwinner,sun5i-a13-mbus-clk"; - reg = <0x01c2015c 0x4>; - clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; - clock-output-names = "mbus"; - }; - /* * The following two are dummy clocks, placeholders * used in the gmac_tx clock. The gmac driver will @@ -736,14 +206,14 @@ * The actual TX clock rate is not controlled by the * gmac_tx clock. */ - mii_phy_tx_clk: clk@2 { + mii_phy_tx_clk: clk@1 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <25000000>; clock-output-names = "mii_phy_tx"; }; - gmac_int_tx_clk: clk@3 { + gmac_int_tx_clk: clk@2 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <125000000>; @@ -757,34 +227,6 @@ clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; clock-output-names = "gmac_tx"; }; - - /* - * Dummy clock used by output clocks - */ - osc24M_32k: clk@1 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <750>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "osc24M_32k"; - }; - - clk_out_a: clk@01c201f0 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-out-clk"; - reg = <0x01c201f0 0x4>; - clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; - clock-output-names = "clk_out_a"; - }; - - clk_out_b: clk@01c201f4 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-out-clk"; - reg = <0x01c201f4 0x4>; - clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; - clock-output-names = "clk_out_b"; - }; }; soc@01c00000 { @@ -841,7 +283,7 @@ compatible = "allwinner,sun4i-a10-dma"; reg = <0x01c02000 0x1000>; interrupts = ; - clocks = <&ahb_gates 6>; + clocks = <&ccu CLK_AHB_DMA>; #dma-cells = <2>; }; @@ -849,7 +291,7 @@ compatible = "allwinner,sun4i-a10-nand"; reg = <0x01c03000 0x1000>; interrupts = ; - clocks = <&ahb_gates 13>, <&nand_clk>; + clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 3>; dma-names = "rxtx"; @@ -862,7 +304,7 @@ compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; interrupts = ; - clocks = <&ahb_gates 20>, <&spi0_clk>; + clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 27>, <&dma SUN4I_DMA_DEDICATED 26>; @@ -877,7 +319,7 @@ compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c06000 0x1000>; interrupts = ; - clocks = <&ahb_gates 21>, <&spi1_clk>; + clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 9>, <&dma SUN4I_DMA_DEDICATED 8>; @@ -892,7 +334,7 @@ compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; interrupts = ; - clocks = <&ahb_gates 17>; + clocks = <&ccu CLK_AHB_EMAC>; allwinner,sram = <&emac_sram 1>; status = "disabled"; }; @@ -908,10 +350,10 @@ mmc0: mmc@01c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; - clocks = <&ahb_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; + clocks = <&ccu CLK_AHB_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; clock-names = "ahb", "mmc", "output", @@ -925,10 +367,10 @@ mmc1: mmc@01c10000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; - clocks = <&ahb_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; + clocks = <&ccu CLK_AHB_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; clock-names = "ahb", "mmc", "output", @@ -942,10 +384,10 @@ mmc2: mmc@01c11000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; - clocks = <&ahb_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; + clocks = <&ccu CLK_AHB_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; clock-names = "ahb", "mmc", "output", @@ -959,10 +401,10 @@ mmc3: mmc@01c12000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c12000 0x1000>; - clocks = <&ahb_gates 11>, - <&mmc3_clk 0>, - <&mmc3_clk 1>, - <&mmc3_clk 2>; + clocks = <&ccu CLK_AHB_MMC3>, + <&ccu CLK_MMC3>, + <&ccu CLK_MMC3_OUTPUT>, + <&ccu CLK_MMC3_SAMPLE>; clock-names = "ahb", "mmc", "output", @@ -976,7 +418,7 @@ usb_otg: usb@01c13000 { compatible = "allwinner,sun4i-a10-musb"; reg = <0x01c13000 0x0400>; - clocks = <&ahb_gates 0>; + clocks = <&ccu CLK_AHB_OTG>; interrupts = ; interrupt-names = "mc"; phys = <&usbphy 0>; @@ -991,9 +433,11 @@ compatible = "allwinner,sun7i-a20-usb-phy"; reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; reg-names = "phy_ctrl", "pmu1", "pmu2"; - clocks = <&usb_clk 8>; + clocks = <&ccu CLK_USB_PHY>; clock-names = "usb_phy"; - resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; status = "disabled"; }; @@ -1002,7 +446,7 @@ compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; reg = <0x01c14000 0x100>; interrupts = ; - clocks = <&ahb_gates 1>; + clocks = <&ccu CLK_AHB_EHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; @@ -1012,7 +456,7 @@ compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; reg = <0x01c14400 0x100>; interrupts = ; - clocks = <&usb_clk 6>, <&ahb_gates 2>; + clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; @@ -1022,7 +466,7 @@ compatible = "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = ; - clocks = <&ahb_gates 5>, <&ss_clk>; + clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; clock-names = "ahb", "mod"; }; @@ -1030,7 +474,7 @@ compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; interrupts = ; - clocks = <&ahb_gates 22>, <&spi2_clk>; + clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 29>, <&dma SUN4I_DMA_DEDICATED 28>; @@ -1045,7 +489,7 @@ compatible = "allwinner,sun4i-a10-ahci"; reg = <0x01c18000 0x1000>; interrupts = ; - clocks = <&pll6 0>, <&ahb_gates 25>; + clocks = <&ccu CLK_AHB_SATA>; status = "disabled"; }; @@ -1053,7 +497,7 @@ compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; reg = <0x01c1c000 0x100>; interrupts = ; - clocks = <&ahb_gates 3>; + clocks = <&ccu CLK_AHB_EHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; @@ -1063,7 +507,7 @@ compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; reg = <0x01c1c400 0x100>; interrupts = ; - clocks = <&usb_clk 7>, <&ahb_gates 4>; + clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; @@ -1073,7 +517,7 @@ compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c1f000 0x1000>; interrupts = ; - clocks = <&ahb_gates 23>, <&spi3_clk>; + clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 31>, <&dma SUN4I_DMA_DEDICATED 30>; @@ -1084,11 +528,20 @@ num-cs = <1>; }; + ccu: clock@01c20000 { + compatible = "allwinner,sun7i-a20-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + pio: pinctrl@01c20800 { compatible = "allwinner,sun7i-a20-pinctrl"; reg = <0x01c20800 0x400>; interrupts = ; - clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -1365,7 +818,7 @@ compatible = "allwinner,sun4i-a10-spdif"; reg = <0x01c21000 0x400>; interrupts = ; - clocks = <&apb0_gates 1>, <&spdif_clk>; + clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; clock-names = "apb", "spdif"; dmas = <&dma SUN4I_DMA_NORMAL 2>, <&dma SUN4I_DMA_NORMAL 2>; @@ -1375,7 +828,7 @@ ir0: ir@01c21800 { compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 6>, <&ir0_clk>; + clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; clock-names = "apb", "ir"; interrupts = ; reg = <0x01c21800 0x40>; @@ -1384,7 +837,7 @@ ir1: ir@01c21c00 { compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 7>, <&ir1_clk>; + clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; clock-names = "apb", "ir"; interrupts = ; reg = <0x01c21c00 0x40>; @@ -1396,7 +849,7 @@ compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c22000 0x400>; interrupts = ; - clocks = <&apb0_gates 4>, <&i2s1_clk>; + clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>; clock-names = "apb", "mod"; dmas = <&dma SUN4I_DMA_NORMAL 4>, <&dma SUN4I_DMA_NORMAL 4>; @@ -1409,7 +862,7 @@ compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c22400 0x400>; interrupts = ; - clocks = <&apb0_gates 3>, <&i2s0_clk>; + clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; clock-names = "apb", "mod"; dmas = <&dma SUN4I_DMA_NORMAL 3>, <&dma SUN4I_DMA_NORMAL 3>; @@ -1429,7 +882,7 @@ compatible = "allwinner,sun7i-a20-codec"; reg = <0x01c22c00 0x40>; interrupts = ; - clocks = <&apb0_gates 0>, <&codec_clk>; + clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; clock-names = "apb", "codec"; dmas = <&dma SUN4I_DMA_NORMAL 19>, <&dma SUN4I_DMA_NORMAL 19>; @@ -1447,7 +900,7 @@ compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c24400 0x400>; interrupts = ; - clocks = <&apb0_gates 8>, <&i2s2_clk>; + clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>; clock-names = "apb", "mod"; dmas = <&dma SUN4I_DMA_NORMAL 6>, <&dma SUN4I_DMA_NORMAL 6>; @@ -1468,7 +921,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 16>; + clocks = <&ccu CLK_APB1_UART0>; status = "disabled"; }; @@ -1478,7 +931,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 17>; + clocks = <&ccu CLK_APB1_UART1>; status = "disabled"; }; @@ -1488,7 +941,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 18>; + clocks = <&ccu CLK_APB1_UART2>; status = "disabled"; }; @@ -1498,7 +951,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 19>; + clocks = <&ccu CLK_APB1_UART3>; status = "disabled"; }; @@ -1508,7 +961,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 20>; + clocks = <&ccu CLK_APB1_UART4>; status = "disabled"; }; @@ -1518,7 +971,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 21>; + clocks = <&ccu CLK_APB1_UART5>; status = "disabled"; }; @@ -1528,7 +981,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 22>; + clocks = <&ccu CLK_APB1_UART6>; status = "disabled"; }; @@ -1538,7 +991,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 23>; + clocks = <&ccu CLK_APB1_UART7>; status = "disabled"; }; @@ -1546,7 +999,7 @@ compatible = "allwinner,sun4i-a10-ps2"; reg = <0x01c2a000 0x400>; interrupts = ; - clocks = <&apb1_gates 6>; + clocks = <&ccu CLK_APB1_PS20>; status = "disabled"; }; @@ -1554,7 +1007,7 @@ compatible = "allwinner,sun4i-a10-ps2"; reg = <0x01c2a400 0x400>; interrupts = ; - clocks = <&apb1_gates 7>; + clocks = <&ccu CLK_APB1_PS21>; status = "disabled"; }; @@ -1563,7 +1016,7 @@ "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; interrupts = ; - clocks = <&apb1_gates 0>; + clocks = <&ccu CLK_APB1_I2C0>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -1574,7 +1027,7 @@ "allwinner,sun4i-a10-i2c"; reg = <0x01c2b000 0x400>; interrupts = ; - clocks = <&apb1_gates 1>; + clocks = <&ccu CLK_APB1_I2C1>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -1585,7 +1038,7 @@ "allwinner,sun4i-a10-i2c"; reg = <0x01c2b400 0x400>; interrupts = ; - clocks = <&apb1_gates 2>; + clocks = <&ccu CLK_APB1_I2C2>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -1596,7 +1049,7 @@ "allwinner,sun4i-a10-i2c"; reg = <0x01c2b800 0x400>; interrupts = ; - clocks = <&apb1_gates 3>; + clocks = <&ccu CLK_APB1_I2C3>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -1607,7 +1060,7 @@ "allwinner,sun4i-a10-can"; reg = <0x01c2bc00 0x400>; interrupts = ; - clocks = <&apb1_gates 4>; + clocks = <&ccu CLK_APB1_CAN>; status = "disabled"; }; @@ -1616,7 +1069,7 @@ "allwinner,sun4i-a10-i2c"; reg = <0x01c2c000 0x400>; interrupts = ; - clocks = <&apb1_gates 15>; + clocks = <&ccu CLK_APB1_I2C4>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -1627,7 +1080,7 @@ reg = <0x01c50000 0x10000>; interrupts = ; interrupt-names = "macirq"; - clocks = <&ahb_gates 49>, <&gmac_tx_clk>; + clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>; clock-names = "stmmaceth", "allwinner_gmac_tx"; snps,pbl = <2>; snps,fixed-burst; @@ -1644,7 +1097,7 @@ , , ; - clocks = <&ahb_gates 28>; + clocks = <&ccu CLK_AHB_HSTIMER>; }; gic: interrupt-controller@01c81000 { @@ -1657,6 +1110,5 @@ #interrupt-cells = <3>; interrupts = ; }; - }; }; -- git-series 0.9.1