From: Anton Bondarenko <anton.bondarenko.sama@gmail.com>
To: Sascha Hauer <s.hauer@pengutronix.de>
Cc: broonie@kernel.org, b38343@freescale.com,
linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
vladimir_zapolskiy@mentor.com, jiada_wang@mentor.com
Subject: Re: [PATCH v3 1/7] spi: imx: Fix DMA transfer
Date: Thu, 5 Nov 2015 17:51:09 +0100 [thread overview]
Message-ID: <563B88FD.8050702@gmail.com> (raw)
In-Reply-To: <20151105083422.GH8526@pengutronix.de>
On 05.11.2015 09:34, Sascha Hauer wrote:
> On Sun, Nov 01, 2015 at 03:41:35PM +0100, Anton Bondarenko wrote:
>> From: Anton Bondarenko <anton_bondarenko@mentor.com>
>>
>> RX DMA tail data handling doesn't work correctly in many cases with
>> current implementation. It happens because SPI core was setup
>> to generates both RX watermark level and RX DATA TAIL events
>> incorrectly. SPI transfer triggering for DMA also done in wrong way.
>>
>> SPI client wants to transfer 70 words for example. The old DMA
>> implementation setup RX DATA TAIL equal 6 words. In this case
>> RX DMA event will be generated after 6 words read from RX FIFO.
>> The garbage can be read out from RX FIFO because SPI HW does
>> not receive all required words to trigger RX watermark event.
>>
>> New implementation change handling of RX data tail. DMA is used to process
>> all TX data and only full chunks of RX data with size aligned to FIFO/2.
>> Driver is waiting until both TX and RX DMA transaction done and all
>> TX data are pushed out. At that moment there is only RX data tail in
>> the RX FIFO. This data read out using PIO.
>
> Have you looked at the RX_DMA_LENGTH and RXTDEN fields of the DMA
> register? These seem to be for handling the remaining bytes of a DMA
> transfer which do not reach the watermark level. From reading the
> documentation I haven't really understood how it works though.
>
> Sascha
>
A lot of times. Current implementation is trying to use it, but works
incorrectly if length % WML != 0 (which means RX_DMA_LENGTH == 0).
Regards, Anton
next prev parent reply other threads:[~2015-11-05 16:51 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-01 14:41 [PATCH v3 0/7] Improvements for SPI IMX driver for Freescale IMX51, IMX53 and IMX6 Anton Bondarenko
2015-11-01 14:41 ` [PATCH v3 1/7] spi: imx: Fix DMA transfer Anton Bondarenko
2015-11-03 7:08 ` Robin Gong
2015-11-04 21:03 ` Anton Bondarenko
2015-11-05 8:34 ` Sascha Hauer
2015-11-05 16:51 ` Anton Bondarenko [this message]
2015-11-14 10:02 ` Anton Bondarenko
2015-11-01 14:41 ` [PATCH v3 2/7] spi: imx: replace fixed timeout with calculated one Anton Bondarenko
2015-11-05 8:47 ` Sascha Hauer
2015-11-10 20:20 ` Anton Bondarenko
2015-11-11 8:12 ` Sascha Hauer
2015-11-14 10:01 ` Anton Bondarenko
2015-11-01 14:41 ` [PATCH v3 3/7] spi: imx: add support for all SPI word width for DMA transfer Anton Bondarenko
2015-11-14 10:08 ` Anton Bondarenko
2015-11-01 14:41 ` [PATCH v3 4/7] spi: imx: add function to check for IMX51 family controller Anton Bondarenko
2015-11-14 10:06 ` Anton Bondarenko
2015-11-01 14:41 ` [PATCH v3 5/7] spi: imx: Add support for loopback for ECSPI controllers Anton Bondarenko
2015-11-14 10:06 ` Anton Bondarenko
2015-11-01 14:41 ` [PATCH v3 6/7] spi: imx: return error from dma channel request Anton Bondarenko
2015-11-05 8:56 ` Sascha Hauer
2015-11-05 16:00 ` Anton Bondarenko
2015-11-14 10:03 ` Anton Bondarenko
2015-11-14 10:05 ` Anton Bondarenko
2015-11-01 14:41 ` [PATCH v3 7/7] spi: imx: defer spi initialization, if DMA engine is pending Anton Bondarenko
2015-11-05 8:59 ` Sascha Hauer
2015-11-05 16:18 ` Anton Bondarenko
2015-11-14 10:03 ` Anton Bondarenko
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