From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1033046AbbKFJIM (ORCPT ); Fri, 6 Nov 2015 04:08:12 -0500 Received: from mail-wm0-f41.google.com ([74.125.82.41]:33628 "EHLO mail-wm0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030705AbbKFJIF (ORCPT ); Fri, 6 Nov 2015 04:08:05 -0500 Subject: Re: [PATCH v3] clocksource/drivers/dw_apb_timer_of: Implement ARM delay timer To: Jisheng Zhang , arnd@arndb.de, tglx@linutronix.de References: <1446690726-2024-1-git-send-email-jszhang@marvell.com> Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org From: Daniel Lezcano Message-ID: <563C6DEF.2040905@linaro.org> Date: Fri, 6 Nov 2015 10:07:59 +0100 User-Agent: Mozilla/5.0 (X11; Linux i686; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <1446690726-2024-1-git-send-email-jszhang@marvell.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/05/2015 03:32 AM, Jisheng Zhang wrote: > Implement an ARM delay timer to be used for udelay(). This allows us to > skip the delay loop calibration at boot on Marvell BG2, BG2Q, BG2CD > platforms. And after this patch, udelay() will be unaffected by CPU > frequency changes. > > Note: Although in case there are several possible delay timers, we may > not select the "best" delay timer. Take one Marvell Berlin platform for > example: we have arch timer and dw-apb timer. The arch timer freq is > 25MHZ while the dw-apb timer freq is 100MHZ, current selection would > choose the dw-apb timer. But the dw apb timer is on the APB bus while > arch timer sits in CPU, the cost of accessing the apb timer is higher > than the arch timer. We could introduce "rating" concept to delay > timer, but this approach "brings a lot of complexity and workarounds > in the code for a small benefit" as pointed out by Daniel. > > Later, Arnd pointed out "However, we could argue that this actually > doesn't matter at all, because the entire point of the ndelay()/ > udelay()/mdelay() functions is to waste CPU cycles doing not much at > all, so we can just as well waste them reading the timer register > than spinning on the CPU reading the arch timer more often.", so we > just simply register the dw apb base delay timer. > > Signed-off-by: Jisheng Zhang > --- Applied, thanks! -- Daniel -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog