From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161385AbbKFMZN (ORCPT ); Fri, 6 Nov 2015 07:25:13 -0500 Received: from mail-gw1-out.broadcom.com ([216.31.210.62]:39445 "EHLO mail-gw1-out.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1161339AbbKFMZK (ORCPT ); Fri, 6 Nov 2015 07:25:10 -0500 X-IronPort-AV: E=Sophos;i="5.20,252,1444719600"; d="scan'208";a="79931065" Subject: Re: [PATCH RESEND 0/4] SMP support for Broadcom NSP To: Hauke Mehrtens , Russell King - ARM Linux References: <1446702681-45339-1-git-send-email-kapilh@broadcom.com> <20151105093443.GO8644@n2100.arm.linux.org.uk> <563BBB3A.6010605@hauke-m.de> CC: Rob Herring , Pawel Moll , "Mark Rutland" , Ian Campbell , Kumar Gala , Ray Jui , Scott Branden , Jon Mason , Florian Fainelli , "Gregory Fong" , Lee Jones , Heiko Stuebner , Kever Yang , Maxime Ripard , Olof Johansson , "Paul Walmsley" , Linus Walleij , Chen-Yu Tsai , , , , From: Kapil Hali Message-ID: <563C9C1E.1080202@broadcom.com> Date: Fri, 6 Nov 2015 17:55:02 +0530 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <563BBB3A.6010605@hauke-m.de> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/6/2015 1:55 AM, Hauke Mehrtens wrote: > On 11/05/2015 10:34 AM, Russell King - ARM Linux wrote: >> On Thu, Nov 05, 2015 at 12:51:17AM -0500, Kapil Hali wrote: >>> Hi, >>> >>> This series adds SMP support for Broadcom's Northstar Plus SoC. >>> >>> There are similar SMP enablement methods for many ARMv7 bsed SoCs. >>> BCM NSP SoC, has a typical such mechanism - after power-on, the >>> secondary core is held in a standby state, primary core provides a >>> startup address for the secondary core and wakes it up. Booting of >>> the secondary core is serialized using pen_release global variable. >> >> Why do you need the pen_release stuff? The above implies that you >> have only one secondary core, and you can control when it comes out >> of standby state. >> >> Please, don't assume that the pen_release stuff is any kind of recommended >> or standardised system. It isn't. It's a hack for ARMs evaluation >> platforms. >> > > I tried to remove the pen code because I also thought/hoped that it is > useless, but the 2. CPU did not boot any more after I removed it. I do > not know the internals of SoC, but it looks like this is needed. > > I described it here: > http://www.spinics.net/lists/arm-kernel/msg452178.html > > I removed this comparison and the jump afterwards ("cmp r7, r0") and > the 2. CPU did not boot any more. Is this pen stuff some kind of > workaround for some bug in the silicon? > pen stuff is not a work around for any bug in BCM NSP silicon. It was the mechanism to bring-up SMP on some of the ARM based SoCs and many silicon vendors seem to consider it as a generic mechanism for controlled bring-up of SMP. But as is clear from Russel King's comments, it is not a standardized recommended method. Also, I removed the pen_release method and it works on BCM NSP SoCs. I will add the changes in the next patch set. > Hauke > Thanks, Kapil Hali