From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754653AbbKXPZu (ORCPT ); Tue, 24 Nov 2015 10:25:50 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:14680 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754577AbbKXPZs (ORCPT ); Tue, 24 Nov 2015 10:25:48 -0500 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 24 Nov 2015 07:13:25 -0800 Subject: Re: [PATCH] clk: tegra: Fix bypassing of PLLs To: Tyler Baker References: <1448032264-29622-1-git-send-email-jonathanh@nvidia.com> CC: Peter De Schrijver , Prashant Gaikwad , Michael Turquette , "Stephen Boyd" , Stephen Warren , "Thierry Reding" , Alexandre Courbot , , , "linux-kernel@vger.kernel.org" , Rhyland Klein , "Kevin's boot bot" From: Jon Hunter Message-ID: <56548175.2050104@nvidia.com> Date: Tue, 24 Nov 2015 15:25:41 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [10.21.132.108] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To UKMAIL101.nvidia.com (10.26.138.13) Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Tyler, On 23/11/15 23:18, Tyler Baker wrote: > Hi Jon, > > On 20 November 2015 at 07:11, Jon Hunter wrote: >> The _clk_disable_pll() function will attempt to place a PLL into bypass >> if the TEGRA_PLL_BYPASS is specified for the PLL and then disable the PLL >> by clearing the enable bit. To place the PLL into bypass, the bypass bit >> needs to be set and not cleared. Fix this by setting the bypass bit and >> not clearing it. >> >> Signed-off-by: Jon Hunter > > The kernelci.org bot recently detected a jetson-tk1 boot failure[1][2] > in the tegra tree. This boot failure has only been observed when > booting with a multi_v7_defconfig kernel variant. The bot bisected[3] > this boot failure to this commit, and I confirmed reverting it on top > of the tegra for-next branch resolves the issue. The ramdisk[4] used > for booting is loaded with the modules from the build. It appears to > me that as the modules are being loaded in userspace by eudev the > jetson-tk1 locks up. I've sifted through the console logs a bit, and > found this splat to be most interesting[5]. Can you confirm this > issue on your end? It appears that the crash is occurring when the tegra-devfreq driver is loaded and I have been able to narrow it down to the pllm pll that is causing the problem. If I remove the bypass flag for pllm then I no longer see the problem (see below). However, the bypass bit is valid for this pll and so I need to see if there is another bug lurking in the management of this pll. The pllm has an additional override feature and I see another enable bit. I need to check this code. Cheers Jon commit 1e4a77f9f08b34f63fc1d4768a31edd5070321a7 Author: Jon Hunter Date: Tue Nov 24 15:13:58 2015 +0000 clk: tegra: Don't bypass pllm (TESTING ONLY) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index c7b5f039d283..bf809086c1e6 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -1788,7 +1788,6 @@ struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, pll_params->vco_min = pll_params->adjust_vco(pll_params, parent_rate); - pll_params->flags |= TEGRA_PLL_BYPASS; pll_params->flags |= TEGRA_PLLM; pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); if (IS_ERR(pll))