From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752249AbbKYRtH (ORCPT ); Wed, 25 Nov 2015 12:49:07 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:1206 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751309AbbKYRtE (ORCPT ); Wed, 25 Nov 2015 12:49:04 -0500 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 25 Nov 2015 09:46:17 -0800 Subject: Re: [PATCH] clk: tegra: Fix bypassing of PLLs To: Tyler Baker , Thierry Reding References: <1448032264-29622-1-git-send-email-jonathanh@nvidia.com> <20151125151100.GA31492@ulmo.nvidia.com> CC: Peter De Schrijver , Prashant Gaikwad , Michael Turquette , "Stephen Boyd" , Stephen Warren , Alexandre Courbot , , , "linux-kernel@vger.kernel.org" , Rhyland Klein , "Kevin's boot bot" From: Jon Hunter Message-ID: <5655F489.6080808@nvidia.com> Date: Wed, 25 Nov 2015 17:48:57 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [10.21.132.108] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 25/11/15 15:52, Tyler Baker wrote: > On 25 November 2015 at 07:11, Thierry Reding wrote: >> On Mon, Nov 23, 2015 at 03:18:59PM -0800, Tyler Baker wrote: >>> Hi Jon, >>> >>> On 20 November 2015 at 07:11, Jon Hunter wrote: >>>> The _clk_disable_pll() function will attempt to place a PLL into bypass >>>> if the TEGRA_PLL_BYPASS is specified for the PLL and then disable the PLL >>>> by clearing the enable bit. To place the PLL into bypass, the bypass bit >>>> needs to be set and not cleared. Fix this by setting the bypass bit and >>>> not clearing it. >>>> >>>> Signed-off-by: Jon Hunter >>> >>> The kernelci.org bot recently detected a jetson-tk1 boot failure[1][2] >>> in the tegra tree. This boot failure has only been observed when >>> booting with a multi_v7_defconfig kernel variant. The bot bisected[3] >>> this boot failure to this commit, and I confirmed reverting it on top >>> of the tegra for-next branch resolves the issue. The ramdisk[4] used >>> for booting is loaded with the modules from the build. It appears to >>> me that as the modules are being loaded in userspace by eudev the >>> jetson-tk1 locks up. I've sifted through the console logs a bit, and >>> found this splat to be most interesting[5]. Can you confirm this >>> issue on your end? >> >> Just to close the loop on this: we've discussed this on IRC and came to >> the conclusion that not using the bypass mode is safer (switching into >> and out of bypass can glitch). I've dropped this patch for now and Jon >> will be looking into a second revision of the patch which, in addition >> to fixing bypass (the fix is legit, it just happens to break because of >> the glitch, most likely), will also remove the BYPASS flag setting so >> that bypass will not be used. > > Thanks for the update, I appreciate you guys looking into this issue. > Please CC me on any fixes, I can re-test and give my tested-by. No problem. On 2nd thoughts I am wondering if there is any value in bypassing the PLL when disabling it. I will look into this and see what I find out. Cheers Jon