From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933206AbbLHPDL (ORCPT ); Tue, 8 Dec 2015 10:03:11 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:62994 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932383AbbLHPDJ (ORCPT ); Tue, 8 Dec 2015 10:03:09 -0500 Subject: Re: [PATCH v9 1/4] dt-binding:Documents of the mbigen bindings To: Marc Zyngier , , References: <1448248513-39760-1-git-send-email-majun258@huawei.com> <1448248513-39760-2-git-send-email-majun258@huawei.com> <56606C02.3050702@arm.com> CC: , , , , , , , , , , , , , , , , , , , From: majun Message-ID: <5666F0BF.3010103@huawei.com> Date: Tue, 8 Dec 2015 10:01:19 -0500 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-Version: 1.0 In-Reply-To: <56606C02.3050702@arm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.47.155.29] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.5666F0DC.0124,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 41428116498529ed7e8ef3a3cbc53d5b Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Markļ¼š Do you have any comments about this patch? Thanks! Ma Jun On 2015/12/3 11:21, Marc Zyngier wrote: > On 23/11/15 03:15, MaJun wrote: >> From: Ma Jun >> >> Add the mbigen msi interrupt controller bindings document. >> >> This patch based on Mark Rutland's patch >> https://lkml.org/lkml/2015/7/23/558 >> >> Signed-off-by: Ma Jun >> --- > > Mark, > > Do you mind having a look at this from a DT perspective? > > Thanks, > > M. > >> Documentation/devicetree/bindings/arm/mbigen.txt | 69 ++++++++++++++++++++++ >> 1 files changed, 69 insertions(+), 0 deletions(-) >> create mode 100644 Documentation/devicetree/bindings/arm/mbigen.txt >> >> diff --git a/Documentation/devicetree/bindings/arm/mbigen.txt b/Documentation/devicetree/bindings/arm/mbigen.txt >> new file mode 100644 >> index 0000000..8ae59a9 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/mbigen.txt >> @@ -0,0 +1,69 @@ >> +Hisilicon mbigen device tree bindings. >> +======================================= >> + >> +Mbigen means: message based interrupt generator. >> + >> +MBI is kind of msi interrupt only used on Non-PCI devices. >> + >> +To reduce the wired interrupt number connected to GIC, >> +Hisilicon designed mbigen to collect and generate interrupt. >> + >> + >> +Non-pci devices can connect to mbigen and generate the >> +interrupt by writing ITS register. >> + >> +The mbigen chip and devices connect to mbigen have the following properties: >> + >> +Mbigen main node required properties: >> +------------------------------------------- >> +- compatible: Should be "hisilicon,mbigen-v2" >> +- reg: Specifies the base physical address and size of the Mbigen >> + registers. >> +- interrupt controller: Identifies the node as an interrupt controller >> +- msi-parent: This property has two cells. >> + The 1st cell specifies the ITS this device connected. >> + The 2nd cell specifies the device id. >> +- num-msis:Specifies the total number of interrupt this device has. >> +- #interrupt-cells : Specifies the number of cells needed to encode an >> + interrupt source. The value must be 2. >> + >> + The 1st cell is global hardware pin number of the interrupt. >> + This value depends on the Soc design. >> + >> + The 2nd cell is the interrupt trigger type. >> + The value of this cell should be: >> + 1: rising edge triggered >> + or >> + 4: high level triggered >> + >> +Examples: >> + >> + mbigen_device_gmac:intc { >> + compatible = "hisilicon,mbigen-v2"; >> + reg = <0x0 0xc0080000 0x0 0x10000>; >> + interrupt-controller; >> + msi-parent = <&its_dsa 0x40b1c>; >> + num-msis = <9>; >> + #interrupt-cells = <2>; >> + }; >> + >> +Devices connect to mbigen required properties: >> +---------------------------------------------------- >> +-interrupt-parent: Specifies the mbigen device node which device connected. >> +-interrupts:specifies the interrupt source. >> + The 1st cell is global hardware pin number of the interrupt. >> + This value depends on the Soc design. >> + The 2nd cell is the interrupt trigger type(rising edge triggered or high >> + level triggered) >> + >> +Examples: >> + gmac0: ethernet@c2080000 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + reg = <0 0xc2080000 0 0x20000>, >> + <0 0xc0000000 0 0x1000>; >> + interrupt-parent = <&mbigen_device_gmac>; >> + interrupts = <656 1>, >> + <657 1>; >> + }; >> + >> > >