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Mon, 1 Jun 2020 07:37:52 +0000 Subject: Re: [PATCH] iommu/amd: Fix event counter availability check To: Alexander Monakov , linux-kernel@vger.kernel.org Cc: Joerg Roedel , iommu@lists.linux-foundation.org References: <20200529200738.1923-1-amonakov@ispras.ru> From: Suravee Suthikulpanit Message-ID: <56761139-f794-39b1-4dfa-dfc05fbe5f60@amd.com> Date: Mon, 1 Jun 2020 14:37:46 +0700 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:68.0) Gecko/20100101 Thunderbird/68.8.1 In-Reply-To: <20200529200738.1923-1-amonakov@ispras.ru> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SN4PR0501CA0093.namprd05.prod.outlook.com (2603:10b6:803:22::31) To DM5PR12MB1163.namprd12.prod.outlook.com (2603:10b6:3:7a::18) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from Suravees-MacBook-Pro.local (2405:9800:b521:3edb:253c:7990:e60b:5077) by SN4PR0501CA0093.namprd05.prod.outlook.com (2603:10b6:803:22::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3066.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: 4E57VEbGr6UhP1LoacAIvkaOtQIDz+HIc1ZY9WGE23xANNDQR6A59hdNyvEz7PAwk6Wy0/nwCiVHd1gWf+RVxpfgTCZaGhjt/OiSyQBuGe/HDAGgLG7D9N90kY2tSVwtv7tdkID2nl8Ui3WaYVxtw++ZU+3wTLIFADSXtiWycETjBuwRvQiqgxT+fu7HdK/Oyzu//g4AIGU56xmoQ9TVIBLbrLhx3Vh5atTMGreWY+LKYxLhR7+KpVKwlQvzoVRnbBeGNTfYBPiAtNsMXd+7fqQBGFckb//rusgkrMt8+9kZGzs6Rq1bDknS9bya7gdpeuPA4VTSoh90qi6poLdv78zWMBn05GrNSEDJm6fGtXtvL8I3FM/uoydMt4em7iwKLkWOVCUNRKXJmo3blOxG6dg9G5aITHxUMk4UkCOFx3/dKfWc6oznl+wrSfQfpjU68uce9KqoRubBwZDfw5mNDgyPdLdWILJuGitbvLeRUpem9hVau/D8SNyKBoTCbFG26dSBvjd5kQ8cLf6GNTdwg+yzSHsnKHf0v6NcSeSO97OxFt3UkN+TSqXGXfg6T8k/ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: eed48cd2-2a79-45ab-2834-08d805feb100 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jun 2020 07:37:52.4163 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ZN+/bQmiLszc8SQOs6DMwzWR6SJ6JfVMonsne8GgB76h+bLcIH1uib5WHjg9D4jrJPQaY+ObZ7c2doq/nC7Vjw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1819 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Alexander, On 5/30/20 3:07 AM, Alexander Monakov wrote: > The driver performs an extra check if the IOMMU's capabilities advertise > presence of performance counters: it verifies that counters are writable > by writing a hard-coded value to a counter and testing that reading that > counter gives back the same value. > > Unfortunately it does so quite early, even before pci_enable_device is > called for the IOMMU, i.e. when accessing its MMIO space is not > guaranteed to work. On Ryzen 4500U CPU, this actually breaks the test: > the driver assumes the counters are not writable, and disables the > functionality. > > Moving init_iommu_perf_ctr just after iommu_flush_all_caches resolves > the issue. This is the earliest point in amd_iommu_init_pci where the > call succeeds on my laptop. According to your description, it should just need to be anywhere after the pci_enable_device() is called for the IOMMU device, isn't it? So, on your system, what if we just move the init_iommu_perf_ctr() here: diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c index 5b81fd16f5fa..17b9ac9491e0 100644 --- a/drivers/iommu/amd_iommu_init.c +++ b/drivers/iommu/amd_iommu_init.c @@ -1875,6 +1875,7 @@ static int __init amd_iommu_init_pci(void) ret = iommu_init_pci(iommu); if (ret) break; + init_iommu_perf_ctr(iommu); } /* -- 2.17.1 Does this works? Thanks, Suravee