From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756194AbbLWAqx (ORCPT ); Tue, 22 Dec 2015 19:46:53 -0500 Received: from lucky1.263xmail.com ([211.157.147.132]:38863 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754791AbbLWAqu (ORCPT ); Tue, 22 Dec 2015 19:46:50 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: ykk@rock-chips.com X-FST-TO: linux-arm-kernel@lists.infradead.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: ykk@rock-chips.com X-UNIQUE-TAG: <4af4c75730b824c3668198e209d302e6> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH v11 09/19] phy: Add driver for rockchip Display Port PHY To: Jingoo Han , "'Inki Dae'" , "'Mark Yao'" , "'Heiko Stuebner'" References: <1450236018-1118-1-git-send-email-ykk@rock-chips.com> <1450237257-2208-1-git-send-email-ykk@rock-chips.com> <000901d13cb3$341b6c40$9c5244c0$@com> Cc: "'Thierry Reding'" , "'Krzysztof Kozlowski'" , "'Rob Herring'" , "'Russell King'" , emil.l.velikov@gmail.com, "'Gustavo Padovan'" , "'Kishon Vijay Abraham I'" , javier@osg.samsung.com, "'Andy Yan'" , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org From: Yakir Yang Message-ID: <5679EEF2.1050309@rock-chips.com> Date: Wed, 23 Dec 2015 08:46:42 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <000901d13cb3$341b6c40$9c5244c0$@com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jingoo, Thanks for your respond. On 12/22/2015 08:20 PM, Jingoo Han wrote: > On Wednesday, December 16, 2015 12:41 PM, Yakir Yang wrote: >> Add phy driver for the Rockchip DisplayPort PHY module. This >> is required to get DisplayPort working in Rockchip SoCs. >> >> Signed-off-by: Yakir Yang >> Reviewed-by: Heiko Stuebner >> --- >> Changes in v11: None >> Changes in v10: >> - Fix the wrong macro value of GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK >> BIT(4) -> BIT(20) >> >> Changes in v9: >> - Removed the unused the variable "res" in probe function. (Heiko) >> - Removed the unused head file. >> >> Changes in v8: >> - Fix the mixed spacers on macro definitions. (Heiko) >> - Remove the unnecessary empty line after clk_prepare_enable. (Heiko) >> >> Changes in v7: >> - Simply the commit message. (Kishon) >> - Symmetrical enable/disbale the phy clock and power. (Kishon) >> >> Changes in v6: None >> Changes in v5: >> - Remove "reg" DT property, cause driver could poweron/poweroff phy via >> the exist "grf" syscon already. And rename the example DT node from >> "edp_phy: phy@ff770274" to "edp_phy: edp-phy" directly. (Heiko) >> - Add deivce_node at the front of driver, update phy_ops type from "static >> struct" to "static const struct". And correct the input paramters of >> devm_phy_create() interfaces. (Heiko) >> >> Changes in v4: >> - Add commit message, and remove the redundant rockchip_dp_phy_init() >> function, move those code to probe() method. And remove driver .owner >> number. (Kishon) >> >> Changes in v3: >> - Suggest, add rockchip dp phy driver, collect the phy clocks and >> power control. (Heiko) >> >> Changes in v2: None >> >> drivers/phy/Kconfig | 7 ++ >> drivers/phy/Makefile | 1 + >> drivers/phy/phy-rockchip-dp.c | 151 ++++++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 159 insertions(+) >> create mode 100644 drivers/phy/phy-rockchip-dp.c >> >> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig >> index 7eb5859d..7355819 100644 >> --- a/drivers/phy/Kconfig >> +++ b/drivers/phy/Kconfig >> @@ -319,6 +319,13 @@ config PHY_ROCKCHIP_USB >> help >> Enable this to support the Rockchip USB 2.0 PHY. >> >> +config PHY_ROCKCHIP_DP >> + tristate "Rockchip Display Port PHY Driver" >> + depends on ARCH_ROCKCHIP && OF >> + select GENERIC_PHY >> + help >> + Enable this to support the Rockchip Display Port PHY. >> + >> config PHY_ST_SPEAR1310_MIPHY >> tristate "ST SPEAR1310-MIPHY driver" >> select GENERIC_PHY >> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile >> index 075db1a..b1700cd 100644 >> --- a/drivers/phy/Makefile >> +++ b/drivers/phy/Makefile >> @@ -35,6 +35,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o >> obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o >> obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o >> obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o >> +obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o >> obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o >> obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o >> obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o >> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c >> new file mode 100644 >> index 0000000..3cb3bf8 >> --- /dev/null >> +++ b/drivers/phy/phy-rockchip-dp.c >> @@ -0,0 +1,151 @@ >> +/* >> + * Rockchip DP PHY driver >> + * >> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd. >> + * Author: Yakir Yang >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License as published by >> + * the Free Software Foundation; either version 2 of the License. >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include > Please order these headers alphabetically. > It will enhance the readability. Done, Thanks, - Yakir > Best regards, > Jingoo Han > >> + >> +#define GRF_SOC_CON12 0x0274 >> + >> +#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(20) >> +#define GRF_EDP_REF_CLK_SEL_INTER BIT(4) >> + >> +#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21) >> +#define GRF_EDP_PHY_SIDDQ_ON 0 >> +#define GRF_EDP_PHY_SIDDQ_OFF BIT(5) >> + >> +struct rockchip_dp_phy { >> + struct device *dev; >> + struct regmap *grf; >> + struct clk *phy_24m; >> +}; >> + >> +static int rockchip_set_phy_state(struct phy *phy, bool enable) >> +{ >> + struct rockchip_dp_phy *dp = phy_get_drvdata(phy); >> + int ret; >> + >> + if (enable) { >> + ret = regmap_write(dp->grf, GRF_SOC_CON12, >> + GRF_EDP_PHY_SIDDQ_HIWORD_MASK | >> + GRF_EDP_PHY_SIDDQ_ON); >> + if (ret < 0) { >> + dev_err(dp->dev, "Can't enable PHY power %d\n", ret); >> + return ret; >> + } >> + >> + ret = clk_prepare_enable(dp->phy_24m); >> + } else { >> + clk_disable_unprepare(dp->phy_24m); >> + >> + ret = regmap_write(dp->grf, GRF_SOC_CON12, >> + GRF_EDP_PHY_SIDDQ_HIWORD_MASK | >> + GRF_EDP_PHY_SIDDQ_OFF); >> + } >> + >> + return ret; >> +} >> + >> +static int rockchip_dp_phy_power_on(struct phy *phy) >> +{ >> + return rockchip_set_phy_state(phy, true); >> +} >> + >> +static int rockchip_dp_phy_power_off(struct phy *phy) >> +{ >> + return rockchip_set_phy_state(phy, false); >> +} >> + >> +static const struct phy_ops rockchip_dp_phy_ops = { >> + .power_on = rockchip_dp_phy_power_on, >> + .power_off = rockchip_dp_phy_power_off, >> + .owner = THIS_MODULE, >> +}; >> + >> +static int rockchip_dp_phy_probe(struct platform_device *pdev) >> +{ >> + struct device *dev = &pdev->dev; >> + struct device_node *np = dev->of_node; >> + struct phy_provider *phy_provider; >> + struct rockchip_dp_phy *dp; >> + struct phy *phy; >> + int ret; >> + >> + if (!np) >> + return -ENODEV; >> + >> + dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL); >> + if (IS_ERR(dp)) >> + return -ENOMEM; >> + >> + dp->dev = dev; >> + >> + dp->phy_24m = devm_clk_get(dev, "24m"); >> + if (IS_ERR(dp->phy_24m)) { >> + dev_err(dev, "cannot get clock 24m\n"); >> + return PTR_ERR(dp->phy_24m); >> + } >> + >> + ret = clk_set_rate(dp->phy_24m, 24000000); >> + if (ret < 0) { >> + dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret); >> + return ret; >> + } >> + >> + dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); >> + if (IS_ERR(dp->grf)) { >> + dev_err(dev, "rk3288-dp needs rockchip,grf property\n"); >> + return PTR_ERR(dp->grf); >> + } >> + >> + ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER | >> + GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK); >> + if (ret != 0) { >> + dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret); >> + return ret; >> + } >> + >> + phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops); >> + if (IS_ERR(phy)) { >> + dev_err(dev, "failed to create phy\n"); >> + return PTR_ERR(phy); >> + } >> + phy_set_drvdata(phy, dp); >> + >> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); >> + >> + return PTR_ERR_OR_ZERO(phy_provider); >> +} >> + >> +static const struct of_device_id rockchip_dp_phy_dt_ids[] = { >> + { .compatible = "rockchip,rk3288-dp-phy" }, >> + {} >> +}; >> + >> +MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids); >> + >> +static struct platform_driver rockchip_dp_phy_driver = { >> + .probe = rockchip_dp_phy_probe, >> + .driver = { >> + .name = "rockchip-dp-phy", >> + .of_match_table = rockchip_dp_phy_dt_ids, >> + }, >> +}; >> + >> +module_platform_driver(rockchip_dp_phy_driver); >> + >> +MODULE_AUTHOR("Yakir Yang "); >> +MODULE_DESCRIPTION("Rockchip DP PHY driver"); >> +MODULE_LICENSE("GPL v2"); >> -- >> 1.9.1 >> > > > >