From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759028AbcAUIq0 (ORCPT ); Thu, 21 Jan 2016 03:46:26 -0500 Received: from e32.co.us.ibm.com ([32.97.110.150]:53909 "EHLO e32.co.us.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758970AbcAUIqX (ORCPT ); Thu, 21 Jan 2016 03:46:23 -0500 X-IBM-Helo: d03dlp02.boulder.ibm.com X-IBM-MailFrom: anju@linux.vnet.ibm.com X-IBM-RcptTo: linux-kernel@vger.kernel.org Subject: Re: [PATCH V10 1/4] perf/powerpc: assign an id to each powerpc register To: Michael Ellerman References: <1452508104-16507-1-git-send-email-anju@linux.vnet.ibm.com> <1452508104-16507-2-git-send-email-anju@linux.vnet.ibm.com> <1453286327.14751.17.camel@ellerman.id.au> Cc: khandual@linux.vnet.ibm.com, maddy@linux.vnet.ibm.com, jolsa@redhat.com, dsahern@gmail.com, acme@redhat.com, sukadev@linux.vnet.ibm.com, hemant@linux.vnet.ibm.com, naveen.n.rao@linux.vnet.ibm.com, linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org From: Anju T Message-ID: <56A09AD7.3030801@linux.vnet.ibm.com> Date: Thu, 21 Jan 2016 14:16:15 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.1.0 MIME-Version: 1.0 In-Reply-To: <1453286327.14751.17.camel@ellerman.id.au> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16012108-0005-0000-0000-00001BA2D75D Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wednesday 20 January 2016 04:08 PM, Michael Ellerman wrote: > Hi Anju, > > On Mon, 2016-01-11 at 15:58 +0530, Anju T wrote: > >> The enum definition assigns an 'id' to each register in "struct pt_regs" >> of arch/powerpc. The order of these values in the enum definition are >> based on the corresponding macros in arch/powerpc/include/uapi/asm/ptrace.h. > Sorry one thing ... > >> diff --git a/arch/powerpc/include/uapi/asm/perf_regs.h b/arch/powerpc/include/uapi/asm/perf_regs.h >> new file mode 100644 >> index 0000000..cfbd068 >> --- /dev/null >> +++ b/arch/powerpc/include/uapi/asm/perf_regs.h >> @@ -0,0 +1,49 @@ >> +#ifndef _ASM_POWERPC_PERF_REGS_H >> +#define _ASM_POWERPC_PERF_REGS_H >> + >> +enum perf_event_powerpc_regs { >> + PERF_REG_POWERPC_GPR0, >> + PERF_REG_POWERPC_GPR1, >> + PERF_REG_POWERPC_GPR2, >> + PERF_REG_POWERPC_GPR3, >> + PERF_REG_POWERPC_GPR4, >> + PERF_REG_POWERPC_GPR5, >> + PERF_REG_POWERPC_GPR6, >> + PERF_REG_POWERPC_GPR7, >> + PERF_REG_POWERPC_GPR8, >> + PERF_REG_POWERPC_GPR9, >> + PERF_REG_POWERPC_GPR10, >> + PERF_REG_POWERPC_GPR11, >> + PERF_REG_POWERPC_GPR12, >> + PERF_REG_POWERPC_GPR13, >> + PERF_REG_POWERPC_GPR14, >> + PERF_REG_POWERPC_GPR15, >> + PERF_REG_POWERPC_GPR16, >> + PERF_REG_POWERPC_GPR17, >> + PERF_REG_POWERPC_GPR18, >> + PERF_REG_POWERPC_GPR19, >> + PERF_REG_POWERPC_GPR20, >> + PERF_REG_POWERPC_GPR21, >> + PERF_REG_POWERPC_GPR22, >> + PERF_REG_POWERPC_GPR23, >> + PERF_REG_POWERPC_GPR24, >> + PERF_REG_POWERPC_GPR25, >> + PERF_REG_POWERPC_GPR26, >> + PERF_REG_POWERPC_GPR27, >> + PERF_REG_POWERPC_GPR28, >> + PERF_REG_POWERPC_GPR29, >> + PERF_REG_POWERPC_GPR30, >> + PERF_REG_POWERPC_GPR31, >> + PERF_REG_POWERPC_NIP, >> + PERF_REG_POWERPC_MSR, >> + PERF_REG_POWERPC_ORIG_R3, >> + PERF_REG_POWERPC_CTR, >> + PERF_REG_POWERPC_LNK, >> + PERF_REG_POWERPC_XER, >> + PERF_REG_POWERPC_CCR, > You skipped SOFTE here at my suggestion, because it's called MQ on 32-bit. > > But I've changed my mind, I think we *should* define SOFTE, and ignore MQ, > because MQ is unused. So just add: > > + PERF_REG_POWERPC_SOFTE, Thank you for reviewing the patch. Yes here we can add SOFTE. Thanks Anju > > >> + PERF_REG_POWERPC_TRAP, >> + PERF_REG_POWERPC_DAR, >> + PERF_REG_POWERPC_DSISR, >> + PERF_REG_POWERPC_MAX, >> +}; >> +#endif /* _ASM_POWERPC_PERF_REGS_H */ > cheers >