From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161384AbcBQL1v (ORCPT ); Wed, 17 Feb 2016 06:27:51 -0500 Received: from foss.arm.com ([217.140.101.70]:59758 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1161157AbcBQL1t (ORCPT ); Wed, 17 Feb 2016 06:27:49 -0500 Subject: Re: [PATCH 6/6] ARM64: dts: rockchip: add core dtsi file for rk3399 To: "jianqun.xu" , heiko@sntech.de, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, jwerner@chromium.org, broonie@kernel.org, catalin.marinas@arm.com, will.deacon@arm.com, sboyd@codeaurora.org, linus.walleij@linaro.org, sjoerd.simons@collabora.co.uk References: <1455673992-16469-1-git-send-email-jay.xu@rock-chips.com> <1455674476-16655-1-git-send-email-jay.xu@rock-chips.com> Cc: huangtao@rock-chips.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org From: Marc Zyngier Organization: ARM Ltd Message-ID: <56C4592F.4080608@arm.com> Date: Wed, 17 Feb 2016 11:27:43 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Icedove/38.5.0 MIME-Version: 1.0 In-Reply-To: <1455674476-16655-1-git-send-email-jay.xu@rock-chips.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Xu, On 17/02/16 02:01, jianqun.xu wrote: > From: Xu Jianqun > > Add dtsi file for Rockchip rk3399 SoCs, which includes some > general nodes such as cpu, pmu, cru, gic, amba and so on. > > Change-Id: Ie3b824e8ead967d4cb119d73222b7a198478c29c > Signed-off-by: Xu Jianqun > --- > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 989 +++++++++++++++++++++++++++++++ > 1 file changed, 989 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > new file mode 100644 > index 0000000..eb671f6 > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi [...] > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = > + + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; Please drop these GIC_CPU_MASK_SIMPLE from the interrupt specifiers, they do not mean anything with GICv3. > + clock-frequency = <24000000>; Are you sure you do need this? Can't your firmware be fixed to correctly program CNTFRQ_EL0? > + }; > + > + xin24m: xin24m { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + clock-output-names = "xin24m"; > + }; > + > + gic: interrupt-controller@fee00000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + interrupt-controller; > + > + reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ > + <0x0 0xfef00000 0 0xc0000>, /* GICR */ > + <0x0 0xfff00000 0 0x10000>, /* GICC */ > + <0x0 0xfff10000 0 0x10000>, /* GICH */ > + <0x0 0xfff20000 0 0x10000>; /* GICV */ > + interrupts = > + + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; Same remark about the mask. > + its: interrupt-controller@fee20000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + reg = <0x0 0xfee20000 0x0 0x20000>; > + }; Looks nice. Is there any peripheral capable of generating MSIs on this SoC? Thanks, M. -- Jazz is not dead. It just smells funny...