From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1424413AbcBRBoE (ORCPT ); Wed, 17 Feb 2016 20:44:04 -0500 Received: from regular1.263xmail.com ([211.150.99.135]:53271 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1422803AbcBRBn7 (ORCPT ); Wed, 17 Feb 2016 20:43:59 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: jay.xu@rock-chips.com X-FST-TO: devicetree@vger.kernel.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: jay.xu@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH 6/6] ARM64: dts: rockchip: add core dtsi file for rk3399 To: Heiko Stuebner References: <1455673992-16469-1-git-send-email-jay.xu@rock-chips.com> <1455674476-16655-1-git-send-email-jay.xu@rock-chips.com> <2396201.CBcovI4jc4@phil> Cc: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, jwerner@chromium.org, broonie@kernel.org, catalin.marinas@arm.com, will.deacon@arm.com, sboyd@codeaurora.org, linus.walleij@linaro.org, sjoerd.simons@collabora.co.uk, huangtao@rock-chips.com, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org From: Jianqun Xu Message-ID: <56C521C9.4050906@rock-chips.com> Date: Thu, 18 Feb 2016 09:43:37 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <2396201.CBcovI4jc4@phil> Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ÔÚ 17/02/2016 15:00, Heiko Stuebner дµÀ: > Hi Jianqun, > > Am Mittwoch, 17. Februar 2016, 10:01:16 schrieb jianqun.xu: >> From: Xu Jianqun >> >> Add dtsi file for Rockchip rk3399 SoCs, which includes some >> general nodes such as cpu, pmu, cru, gic, amba and so on. >> >> Change-Id: Ie3b824e8ead967d4cb119d73222b7a198478c29c > > please remove any review-cruft like Change-Ids from mainline patches :-) ok, will fix it in next version patch > >> Signed-off-by: Xu Jianqun >> --- >> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 989 >> +++++++++++++++++++++++++++++++ 1 file changed, 989 insertions(+) >> create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi >> >> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi >> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi new file mode 100644 >> index 0000000..eb671f6 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi >> @@ -0,0 +1,989 @@ >> +/* >> + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd >> + * >> + * This file is dual-licensed: you can use it either under the terms >> + * of the GPL or the X11 license, at your option. Note that this dual >> + * licensing only applies to this file, and not this project as a >> + * whole. >> + * >> + * a) This library is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License as >> + * published by the Free Software Foundation; either version 2 of the >> + * License, or (at your option) any later version. >> + * >> + * This library is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * Or, alternatively, >> + * >> + * b) Permission is hereby granted, free of charge, to any person >> + * obtaining a copy of this software and associated documentation >> + * files (the "Software"), to deal in the Software without >> + * restriction, including without limitation the rights to use, >> + * copy, modify, merge, publish, distribute, sublicense, and/or >> + * sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following >> + * conditions: >> + * >> + * The above copyright notice and this permission notice shall be >> + * included in all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> + * OTHER DEALINGS IN THE SOFTWARE. >> + */ >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +/ { >> + compatible = "rockchip,rk3399"; >> + interrupt-parent = <&gic>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + aliases { >> + serial0 = &uart0; >> + serial1 = &uart1; >> + serial2 = &uart2; >> + serial3 = &uart3; >> + }; >> + >> + psci { >> + compatible = "arm,psci"; >> + method = "smc"; >> + }; >> + >> + cpus { >> + #address-cells = <2>; >> + #size-cells = <0>; >> + >> + cpu-map { >> + cluster0 { >> + core0 { >> + cpu = <&cpu_l0>; >> + }; >> + core1 { >> + cpu = <&cpu_l1>; >> + }; >> + core2 { >> + cpu = <&cpu_l2>; >> + }; >> + core3 { >> + cpu = <&cpu_l3>; >> + }; >> + }; >> + >> + cluster1 { >> + core0 { >> + cpu = <&cpu_b0>; >> + }; >> + core1 { >> + cpu = <&cpu_b1>; >> + }; >> + }; >> + }; >> + >> + idle-states { >> + entry-method = "psci"; >> + >> + cpu_sleep: cpu-sleep-0 { >> + compatible = "arm,idle-state"; >> + }; >> + }; > > why the essentially empty idle-states, which is probably missing properties? > In the absence of a real idle driver the kernel will fall back to > arch_cpu_idle(), which already does WFI handling even on arm64. > the idle node will be added by my colleague with new patch later, so I will remove it first in next version patch. > >> + >> + cpu_l0: cpu@0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + reg = <0x0 0x0>; >> + cpu-idle-states = <&cpu_sleep>; > > that won't compile, as the referenced node is not present > > >> + enable-method = "psci"; >> + }; >> + >> + cpu_l1: cpu@1 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + reg = <0x0 0x1>; >> + cpu-idle-states = <&cpu_sleep>; >> + enable-method = "psci"; >> + }; >> + >> + cpu_l2: cpu@2 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + reg = <0x0 0x2>; >> + cpu-idle-states = <&cpu_sleep>; >> + enable-method = "psci"; >> + }; >> + >> + cpu_l3: cpu@3 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + reg = <0x0 0x3>; >> + cpu-idle-states = <&cpu_sleep>; >> + enable-method = "psci"; >> + }; >> + >> + cpu_b0: cpu@100 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a72", "arm,armv8"; >> + reg = <0x0 0x100>; >> + cpu-idle-states = <&cpu_sleep>; >> + enable-method = "psci"; >> + }; >> + >> + cpu_b1: cpu@101 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a72", "arm,armv8"; >> + reg = <0x0 0x101>; >> + cpu-idle-states = <&cpu_sleep>; >> + enable-method = "psci"; >> + }; >> + }; >> + >> + pmu { >> + compatible = "arm,armv8-pmuv3"; >> + interrupts = ; >> + interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, >> + <&cpu_l3>, <&cpu_b0>, <&cpu_b1>; >> + }; >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = >> + > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > > shouldn't that be GIC_CPU_MASK_SIMPLE(6) instead of 4? > ok, will fix it in next version patch > >> + > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, >> + > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, >> + > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; >> + clock-frequency = <24000000>; >> + }; >> + >> + xin24m: xin24m { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + clock-frequency = <24000000>; >> + clock-output-names = "xin24m"; >> + }; >> + >> + gic: interrupt-controller@fee00000 { >> + compatible = "arm,gic-v3"; >> + #interrupt-cells = <3>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + interrupt-controller; >> + >> + reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ >> + <0x0 0xfef00000 0 0xc0000>, /* GICR */ >> + <0x0 0xfff00000 0 0x10000>, /* GICC */ >> + <0x0 0xfff10000 0 0x10000>, /* GICH */ >> + <0x0 0xfff20000 0 0x10000>; /* GICV */ >> + interrupts = >> + > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > > again GIC_CPU_MASK_SIMPLE(6)? ok. > >> + its: interrupt-controller@fee20000 { >> + compatible = "arm,gic-v3-its"; >> + msi-controller; >> + reg = <0x0 0xfee20000 0x0 0x20000>; >> + }; >> + }; >> + >> + amba { >> + compatible = "arm,amba-bus"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + dmac_bus: dma-controller@ff6d0000 { >> + compatible = "arm,pl330", "arm,primecell"; >> + reg = <0x0 0xff6d0000 0x0 0x4000>; >> + interrupts = , >> + ; >> + #dma-cells = <1>; >> + clocks = <&cru ACLK_DMAC_BUS>; >> + clock-names = "apb_pclk"; > > has the FLUSHP bug gotten fixed? That would be cool. > Since amba node is added by my colleague, I will double check it, thanks > >> + }; > > rest looks nice on first glance :-) > > > Heiko > > >