From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754166AbcBWQS3 (ORCPT ); Tue, 23 Feb 2016 11:18:29 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:17745 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751627AbcBWQS1 (ORCPT ); Tue, 23 Feb 2016 11:18:27 -0500 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 23 Feb 2016 08:18:21 -0800 Subject: Re: [PATCH 2/2] drm/tegra: Set the DMA mask To: Thierry Reding , Alexandre Courbot References: <1456208754-12362-1-git-send-email-acourbot@nvidia.com> <1456208754-12362-2-git-send-email-acourbot@nvidia.com> <20160223160440.GE27656@ulmo> CC: Stephen Warren , , , , X-Nvconfidentiality: public From: Terje Bergstrom Message-ID: <56CC8652.8020208@nvidia.com> Date: Tue, 23 Feb 2016 08:18:26 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <20160223160440.GE27656@ulmo> X-Originating-IP: [172.17.184.28] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL105.nvidia.com (172.20.187.12) Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 02/23/2016 08:04 AM, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Tue, Feb 23, 2016 at 03:25:54PM +0900, Alexandre Courbot wrote: >> The default DMA mask covers a 32 bits address range, but tegradrm >> can address more than that. Set the DMA mask to the actual >> addressable range to avoid the use of unneeded bounce buffers. >> >> Signed-off-by: Alexandre Courbot --- Thierry, >> I am not absolutely sure whether the size is correct and applies to >> all Tegra generations - please let me know if this needs to be >> reworked. >> >> drivers/gpu/drm/tegra/drm.c | 1 + 1 file changed, 1 insertion(+) > > This kind of depends on whether or not the device is behind an IOMMU. > If it is, then the IOMMU DMA MASK would apply, which can be derived > from the number of address bits that the IOMMU can handle. The SMMU > supports 32 address bits on Tegra30 and Tegra114, 34 address bits on > more recent generations. > > I think for now it's safer to leave the DMA mask at the default (32 > bit) to avoid the need to distinguish between IOMMU and non-IOMMU > devices. The GPUs after Tegra114 can choose per access whether they're using IOMMU or not. The interface is 34 bits wide, so the physical addresses can be 34 bits. IOMMU addresses are limited by Tegra SMMU to 32-bit for gk20a. gm20b can use 34-bit if SMMU is configured to combine four ASIDs together.