From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753336AbcCAS3l (ORCPT ); Tue, 1 Mar 2016 13:29:41 -0500 Received: from torg.zytor.com ([198.137.202.12]:41020 "EHLO mail.zytor.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753305AbcCAS3i (ORCPT ); Tue, 1 Mar 2016 13:29:38 -0500 Subject: Re: [PATCH v4 1/5] getcpu_cache system call: cache CPU number of running thread To: Mathieu Desnoyers , Linus Torvalds References: <1456270120-7560-1-git-send-email-mathieu.desnoyers@efficios.com> <1150363257.9781.1456533630895.JavaMail.zimbra@efficios.com> <56D14132.5050100@zytor.com> <2053850250.10158.1456582501604.JavaMail.zimbra@efficios.com> <20160227145809.GD6356@twins.programming.kicks-ass.net> <1401667361.10273.1456617236327.JavaMail.zimbra@efficios.com> <1082926946.10326.1456619994590.JavaMail.zimbra@efficios.com> Cc: Ben Maurer , Thomas Gleixner , Ingo Molnar , Russell King , linux-api , Andrew Morton , Michael Kerrisk , Dave Watson , rostedt , Andy Lutomirski , Will Deacon , "Paul E. McKenney" , Chris Lameter , Andi Kleen , Josh Triplett , Paul Turner , Linux Kernel Mailing List , Catalin Marinas , Andrew Hunter , Peter Zijlstra From: "H. Peter Anvin" Message-ID: <56D5DEA8.3040908@zytor.com> Date: Tue, 1 Mar 2016 10:25:44 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <1082926946.10326.1456619994590.JavaMail.zimbra@efficios.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 02/27/16 16:39, Mathieu Desnoyers wrote: > > Very good points! Would the following interfaces be acceptable ? > > /* This structure needs to be aligned cache line size. */ > struct thread_local_abi { > int32_t cpu_id; /* Aligned on > 32-bit. */ > uint32_t rseq_seqnum; /* Aligned on 32-bit. */ > uint64_t rseq_post_commit_ip; /* Aligned on 64-bit. */ > /* Add new fields at the end. */ > } __attribute__((packed)); > First of all, DO NOT use __attribute__((packed)). First of all, it buggers up the alignment of the *entire structure* (the alignment of a packed structure defaults to 1, and gcc will assume the whole structure is misaligned, generating unaligned access instructions on architectures which need them.) Sadly gcc doesn't currently have an __attribute__ to express "error out on padding" which is what you actually want here. You may, however, want to add an explicit alignment attribute to make sure it is cache line aligned. Second, as far as the 32/64 bit issue is concerned, you have to order the fields so you always access the LSB. This is probably the best way to do it: #ifdef __LP64__ # define __FIELD_32_64(field,n) uint64_t field; #elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ # define __FIELD_32_64(field,n) uint32_t field, _unused ## n; #else # define __FIELD_32_64(field,n) uint32_t _unused ## n, field; #endif All these macros are intrinsic to gcc (and hopefully to gcc-compatible compilers) so there are no header file dependencies. -hpa