From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757849AbcDAH0E (ORCPT ); Fri, 1 Apr 2016 03:26:04 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:16200 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751923AbcDAH0C convert rfc822-to-8bit (ORCPT ); Fri, 1 Apr 2016 03:26:02 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 01 Apr 2016 00:24:41 -0700 Message-ID: <56FE2009.4020302@nvidia.com> Date: Fri, 1 Apr 2016 12:45:21 +0530 From: Laxman Dewangan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: Mark Brown CC: Bjorn Andersson , Bjorn Andersson , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Liam Girdwood , Stephen Warren , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Gandhar Dighe , Stuart Yates Subject: Re: [PATCH 1/2] regulator: DT: Add support to scale ramp delay based on platform behavior References: <20160331174741.GO2350@sirena.org.uk> <56FD62BA.3040406@nvidia.com> <20160331183130.GR2350@sirena.org.uk> <56FD6CF7.5080909@nvidia.com> <20160331184553.GS2350@sirena.org.uk> <56FD6ED6.3020507@nvidia.com> <20160331185945.GT2350@sirena.org.uk> <56FD7379.2000307@nvidia.com> <20160331192227.GU2350@sirena.org.uk> <56FD7F07.7010404@nvidia.com> <20160331203942.GV2350@sirena.org.uk> In-Reply-To: <20160331203942.GV2350@sirena.org.uk> X-Originating-IP: [10.19.65.30] X-ClientProxiedBy: DRUKMAIL102.nvidia.com (10.25.59.20) To bgmail102.nvidia.com (10.25.59.11) Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Friday 01 April 2016 02:09 AM, Mark Brown wrote: > * PGP Signed by an unknown key > > On Fri, Apr 01, 2016 at 01:18:23AM +0530, Laxman Dewangan wrote: >> On Friday 01 April 2016 12:52 AM, Mark Brown wrote: >> So as per above, it will be adjusted to 13.75mV/us (nearest higher side) for >> device configuration but this device need to configure for 27.5mV/us. > You're saying that the device is so bad at regulating the ramp rate that > it's not only failing to keep up with the desired ramp rate and capping > at whatever rate but it's also doing even worse if configured for a > slower rate? That's not great, it sounds like it's doing the ramp > control via some sort of dead reckoning thing rather than by actually > ramping the voltage it's trying to regulate like it was asked to. > > Is the error in the observed values a function of the capacitance that > we can calcuate here? > As per datasheet, There is no direct equation for ramp time deviation when regulator output current cross the regulator current limit. From data sheet: /** During a DVS transition, the regulators output current will increase by COUT*dV/dt. In the event that the load current plus the additional current imposed by the DVS transition, reach the regulator’s current limit, the current limit will be enforced. When the current limit is enforced, the advertised DVS transition rate (dV/dt) will not occur. And there is calculation of Iinrush based on Cout and configured dv/dt. Iinrush=min(Ilim & Cout*dV/dt). IINRUSH calculation for Cout = 100uF IINRUSH=min(ILIMP & COUT*dV/dt). SD0 is a two phase regulator with a typical PMOS current limit (ILIMPP0) of 3.75A per phase. For ILIMP in the above equation we will use 2x3.75A=7.5A. SD0 has a typical soft-start rate (dV/dt_SS_SD0) of 25mV/us. For dv/dt in the above equation we will use 25mV/us. IINRUSH=min(7.5A & 100uF*25mV/us). IINRUSH=min(7.5A & 2.5A). IINRUSH=2.5A **/ So providing configured and observed value direct will help much here.